105895411AN-260| Application Note
a
AN-260 APPLICATION NOTE
One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 781/329-4700 World Wide Web Site: http://www.analog.com
Using Digitally Programmable Delay Generators
by Allen Hill, IED
The AD9500 and AD9501 digitally programmable delay generators are versatile parts, useful in numerous applications. The parts are designed for use in automatic test equipment as a deskew element for digital data lines. The versatility of the AD9500 and AD9501 for generating programmable delays allows them to be used in applications that range from ATE to communications, computers, disk drives, lasers and ultrasound systems. This note describes how best to apply these parts in some of these applications. GENERAL DESCRIPTION A digitally programmable delay generator delays a digital edge by a programmed amount of time. Figure 1 shows the basic function of a programmable delay generator. The delay through the device is controlled by an N-bit digital word. This is the programmed delay. A trigger pulse is applied to the input, and after a fixed propagation delay (tPD), the pulse edge appears a program delay later at the output.
DIGITAL DELAY VALUE TRIGGER N DELAY GENERATOR OUTPUT
comparator threshold set by the DAC, the output of the comparator switches. This output is delayed from the trigger pulse by an amount of time that is proportional to the DAC digital input code and the slope of the ramp. Altering the digital delay value changes the DAC output voltage, which alters the delay through the circuit. The slope of the ramp is controlled with external components.
TRIGGER RESET TIMING CONTROL FLIP-FLOP RAMP GENERATOR
DELAYED OUTPUT
DIGITAL DELAY VALUE TRIGGER
N
LATCH
N
D/A CONVERTER
COMPARATOR
DELAYED OUTPUT RESET
RAMP VOLTAGE DAC VOLTAGE
(DAC CODE 00 HEX)
TRIGGER PULSE OUTPUT PULSE
(DAC CODE FF HEX)
Figure 2. Delay Generator Block Diagram and Basic Timing
tPD
PROGRAM DELAY
Figure 1. Programmable Delay Generator
The AD9500 (ECL) and AD9501 (TTL) use a ramp/comparator/DAC architecture as shown in Figure 2. One input of a high speed comparator is driven by a digitalto-analog converter (DAC). The DAC is used to set a reference voltage at this comparator input. The other input is connected to a ramp generator. The ramp generator is started by applying a pulse to the trigger input of the delay generator. When the ramp voltage crosses the
Once the comparator has switched, the ramp generator and comparator must be reset so that the device can be triggered again. One method of accomplishing the reset is to connect the output of the delay generator to the reset pin. This results in an output pulsewidth that is equal to the reset propagation delay of the device (7 ns to 15 ns). An alternate, and versatile, method of resetting the device is to use an external signal that meets the timing requirements of the part. An external reset signal allows the pulsewidth to be controlled and makes system integration of the delay signal easier.
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