370462715384546645EE01D_sch| Application Note
6
5
DO NOT INSTALL +5VA DC COUPLED ENCODE OPTION (SEE NOTE 3)
4
3
2
+3P3VD
1
C6 0.01U
5 1 +5VA +5VA BUFLAT 2
+V
U6
GND
4 NC7SZ32 39 37 J2 HEADER40 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
U8 R1 100 1 NC 2 D 3 C5 0.01U D 4 VBB Q VEE 5 R12 100 C33 0.1U C34 0.1U R14 100 Q 6
(SEE NOTE 4) 1 2 3 4 5 ENC
8 VCC 7
3 R11 66.5 R13 66.5 U7 1
RN1 16 15 14 13 12 11 10 9 100
+3P3VD 20
RN2
D
OUT_EN D0 D1 D2 D3 D4 D5 D6 D7 GND
VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CLOCK
35
16 15 14 13 12 11 10 9
D
2 3 4 5 6 7 8 9 10
19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8
B13 B12 B11 B10 B09 B08 B07 B06 B05 B04
33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
MC100LVEL16
ENC
J4 C4 0.1U 3
OPTIONAL
4 T2 5 6 1 C29 0.1U 2 3 CR1
6 7 8 ENC
2
R35
1
1
49.9
ADT4-1WT 4:1 IMPEDANCE RATIO
BUFLAT 100 +3P3VD
+5VA Y1 1
3
VREF 1
74LCX574 U2
RN3
B03 B02
RN4 1 2 3 4 5 6 7 8 9 16 15 14 13 12 11 10
OE
VCC
14
12 10
F3 1 C22 0.1U +3P3V_XTL F5 1 C15 0.1U 2 +3P3V U1 1
52 51 50 49 48 47 46 45
OUT_EN D0 D1 D2 D3 D4 D5 D6 D7 GND
VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CLOCK
20 19 18 17 16 15 14 13 12 11
2
DR_OUT
C32 0.1U
1
16 15 14 13 12 11 10 9 100
2 3 4 5 6 7 8 9 10
B01 B00
+3P3V
OE' VCC' GND'OUT' 7 GND OUT
C
5
GND
2 3 4
C
8
66.66MHz (AD6644) 80MHz (AD6645)
44 D6
43 DVCC
42 GND
41 D5
40 D4
39
5 6
D9
D8
D13
D12
D11
DRY
D10
D7
+3P3V +3P3VD
DVCC GND VREF
D3
38
7 8 37 36
2
3
D2 D1 D0
35
OPT_CLK
J3 C3 0.1U
E2 BUFLAT 100 OVR E6
R10 500 1 2
+V
5 U4
GND
INSTALL JUMPER
4 5
GND ENC ENC GND AVCC AVCC GND AIN AIN GND AVCC AVCC AVCC AVCC GND GND GND GND GND GND
4
OPT_LAT BUFLAT DR_OUT +5VA E1
DMID
34
1
PREF
74LCX574 F4 1 +3P3VD C23 0.1U C24 0.1U C25 0.1U C26 0.1U
6 7 8 9 10
DO NOT INSTALL
R9 500
NC7SZ32
3
GND
33
2
AD6644/AD6645
DVCC OVR DNC AVCC GND AVCC GND AVCC 32 31 30 29 +5VA
+3P3V
DC COUPLED AIN OPTION (SEE NOTE 2)
+5VA
0.0
DO NOT INSTALL
C27
11
12
F2
+3P3VIN
+3P3V C1 10U C9 0.1U C10 0.1U C11 0.01U C12 0.01U C13 0.01U C14 0.01U
B
R4
2 1
28 27
+5VA
B
13
499 -5V VREF
C1
1
R8 499
6
V-
C2
J1 1
+5V
2
VAL
R7 25.5
1 2
14
AIN
15
16
17
18
19
20
21
22
23
24
25
26 2 3
F1 C2
+3P3VIN
+5VA
+5VA
+5VA
+5VA
+5VA
8
NC
V+
5
1 2
+5VA
AD8138ARM U3
VOCM
4
C16 0.1U
C17 0.01U
C18 0.01U
C19 0.01U
C20 0.01U
C21 0.01U
AIN R6 25.5
C8 0.1U
C7 0.1U
4
5 6
10U
AIN
J5 R3 499 +5VA
7
-5V
+3P3V_XTL
3
1
R5 499
1
R15 178
(SEE NOTE 1)
2
C31 C40 10U 0.01U 0.1U 10U C39 C38
R2
C28
60.4
(SEE NOTE 1) DO NOT INSTALL
2
0.0
L1
1 T3 3
6 5 4 C30 0.1U
NOTES: 1. R2 IS INSTALLED FOR INPUT MATCHING ON THE PRIMARY OF T3. R15 IS NOT INSTALLED. R15 IS INSTALLED FOR INPUT MATCHING ON THE SECONDARY OF T3, R2 IS NOT INSTALLED. 2. AC COUPLED AIN IS STANDARD, R3, R4, R5, R8 & U3 ARE NOT INSTALLED. IF DC COUPLED AIN IS REQUIRED, C30, R15 & T3 ARE NOT INSTALLED. 3. AC COUPLED ENCODE IS STANDARD. C5, C6, C33, C34, R1, R11-R14 & U8 ARE NOT INSTALLED. IF PECL ENCODE IS REQUIRED, CR1 & T3 ARE NOT INSTALLED.
A
4.7NH
A
ADT4-1WT 4:1 IMPEDANCE RATIO
Analog Devices
DRS-HSC
7910 Triad Center Dr. Greensboro, NC 27409
AD6644ST/AD6645SQ PCB Evaluation Board Schematic Filename: 6645EE01D Rev: D JBB JCP
Date:
6 5 4 3 2
9-27-2005_13:27
Sheet 1
1
of
1
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