499594169539373252848419AN_798_0| Application Note

499594169539373252848419AN_798_0 PDF

499594169539373252848419AN_798_0| Application Note


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AN-798 APPLICATION NOTE

Using the PWM to Generate Analog Output on the ADuC702x Family
by Aude Richard

INTRODUCTION The ADuC702x family integrates a 32-bit ARM7TDMI microcontroller and high precision analog blocks. Depending on the model, up to four 12-bit DACs are available. In some applications where more analog output is required, the PWM can also be used as a low resolution DAC. This application note describes how to generate an extra analog output from a PWM. THEORY A typical PWM signal is shown in Figure 1. The base frequency (or switching frequency) is fixed and the pulse width (duty cycle) is variable.

side. The duty cycle of Channel 0 is programmed via the PWMCH0 register. It can be modified at each PWM period, during a synchronization interrupt. In the following example, a sine wave will be generated using the PWM0H output on P3.0. On the high side output, the duty cycle is only programmable between 50% and 100%, but using the crossover option (in PWMEN MMR) allows switching internally between 0L and 0H resulting in a duty cycle between 0 and 50%.

Figure 1. Typical PWM Waveform The pulse width is proportional to the amplitude of the signal, while the frequency of the waveform is constant. PWM BLOCK ON THE ADuC702x The PWM block on the ADuC702x consists of three PWM channels. These three PWMs have a common switching frequency programmable between 343.99 Hz and 11.27 MHz in the PWMDAT0 register. The switching frequency (fPWM) is calculated as follows: fPWM = f CORE /(2 PWMDAT0) The switching frequency is set to 5.5 kHz, or PWMDAT0 = 0x1000. This results in a sine wave at 86 Hz (64 samples per sine wave). The duty cycle of each channel is independent, therefore the three phases can be used as three independent PWMs. In this application note, one channel of the PWM block, Channel 0, is discussed. Each PWM channel has two outputs: a high side and a low side. The duty cycle is programmable from 50% to 100% on the high side and 50% to 0% on the low

Figure 2. Single Update Mode Timing The formulas to calculate the value in the PWMA register are as follows: On the high side: T0HH = PWMDAT0 + 2(PWMCH0 PWMDAT1) tCORE T0HL = PWMDAT0 2(PWMCH0 PWMDAT1) tCORE Or dOH = 1/2 + (PWMCH0 PWMDAT1) / PWMDAT0 Considering no dead time is being used: PWMCH0 = (dOH 1/2 ) PWMDAT0 On the low side: T0LH = PWMDAT0 2(PWMCH0 + PWMDAT1) tCORE T0LL = PWMDAT0 + 2(PWMCH0 + PWMDAT1) tCORE Or dOL = 1/2 (PWMCH0 + PWMDAT1) / PWMDAT0 Considering no dead time is being used: PWMCH0 = (1/2 dOL) x PWMDAT0

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