529745542335562842692325AnalogDevices_Reprint| Application Note
Special Feature
SHARC Bites Back
From the Editor's Files:
This is the 2nd in a series of articles that explores the complex processor tradeoffs and evaluations required to choose the most effective processor for continuous real-time signal processing applications as typified by the 1024-point complex Fast Fourier Transform (cFFT). Part I appeared in the December 2002 issue of COTS Journal, and is available on www.cotsjournalonline.com.
Part II: Continuous Real-Time Signal Processing-- Comparing TigerSHARC and PowerPC Via Continuous cFFTs
Continuous, measured benchmarks provide the only real insight into realworld DSP performance. An analysis using continuous cFFTs sheds light on the real performance differences between TigerSHARC and PowerPC.
Jeffry Milrod, President, BittWare Chuck Millet, TigerSHARC Product Manager, Analog Devices
A
lthough often quoted, peak performance benchmarks are misleading when used to depict DSP performance. Any realworld view into DSP performance should center on sustained or continuous, algorithm performance. Part I of this article series illustrated that fact. It also proposed the continuous 1024-point cFFT algorithm as an excellent indicator of realworld performance. The Analog Devices TigerSHARC (ADSPTS101) and the Motorola G4 PowerPC with Altivec (MPC7410 and MPC7455) processors were compared along those lines, with predictions made for their performance.
Here, that analysis is taken a step further. BittWare engineers took continuous 1024-point cFFT algorithm benchmarks and coded, optimized and measured them on the ADSPTS101 at 250 MHz and on the MPC7410 at 400 MHz. Unlike some other "system-level" benchmarks, these implementations of the continuous cFFT benchmarks took advantage of all the features of each processor that could improve performance--since this approach is more like what would be implemented by an engineer designing a real system. The results are reported in detail, along with extrapolations for other variants and speeds, as well as boardlevel implications.
TigerSHARC Implementation
The continuous cFFT algorithm was implemented on a BittWare Tiger-PCI board (TSPC) that features a cluster of four ADSP-TS101 TigerSHARCs running at 250 MHz. The benchmark code was written in C and was developed using Analog Devices' VisualDSP++. Part I of the article series predicted that running continuous cFFTs on the TigerSHARC would be processor-limited, implying that the continuous benchmark performance would be driven by the performance of the cFFT algorithm itself. That drove the engineers to choose a highly optimized cFFT routine for the benchmark. With that in mind, the
Reprinted from COTS Journal December 2003
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