53864374967227AN_790_0| Application Note
One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 Tel: 781/329-4700 Fax: 781/461-3113 www.analog.com
AN-790 APPLICATION NOTE
How to Use the ADV202
by Christine Bako
INTRODUCTION This application note gives an overview of the architecture of the ADV202 and its functional blocks. It explains data flows in encode and decode modes, and what interfaces to use for uncompressed data input and compressed data output. An overview of how the HDATA bus can be configured for compressed data output or HIPI mode is also discussed. This application note also includes a synopsis of what is required to configure the ADV202 and an application-specific overview for standard definition, high definition, and still image applications. ADV202 ARCHITECTURE
Host interface can be configured for 32- bit or 16 -bit control and 8-, 16 -, or 32-bit data. Controls data transfers between FIFOs and controls two external DMA channels. Controls access to indirect and direct register. Pixel interface is used to process video or pixel data transfers from/to VDATA or HDATA bus. Internal DMA engine. Used to facilitate fast internal memory-to-memory data transfers.
Data Flow in Encode and Decode Mode
Figure 2. ADV202 Encode Mode--1 Video or pixel data can be input over the VDATA bus or, alternatively, pixel data can be input over the HDATA bus. In either case the video/pixel data is passed to the pixel interface. The data is then deinterleaved and passed to the wavelet transform engine. The input data, organized in tiles or frames, is then decomposed into subbands using 5/3 or 9/7 wavelet filters. The wavelet transform (WT) can perform up to six wavelet decomposition levels on a tile /frame. The resultant wavelet coefficients are then written to internal memory. The ADV202 does not have any field buffers to perform compression. The wavelet coefficients are computed on a line by line basis and the entire wavelet coefficients are stored in internal memory.
Figure 1. Block Diagram of the ADV202 Block Diagram and Functional Description The ADV202 contains the following main functional blocks: An embedded 32-bit RISC processor serves as a system controller. The RISC processor includes its own ROM and RAM for both program and data memory. Wavelet transform engine with 5/3 and 9/7 wavelet filters giving up to six transform levels. Three entropy codecs (ECs) generate JPEG2000 code stream using quantization, rate distortion optimization, and context modeling, and organize data into packets and layers. The three ECs can guarantee a throughput of up to 65 MSPS.
REV. 0
53864374967227AN_790_0 Application Note analog Download PDF
Add this permalink to your bookmarks for future download of 53864374967227AN_790_0 ApplicationNote
Permalink: http://application.emcelettronica.com/analog/53864374967227AN_790_0
