5502087428059AN777_0| Application Note
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AN-777 APPLICATION NOTE
Dual AD9884A Design Guideline to Achieve UXGA Resolutions
by Del Jones
INTRODUCTION Pixel clock speeds in excess of 140 MHz can be achieved with the AD9884A by using a dual chip "ping-pong" configuration. A dual chip solution is different from an alternate pixel sampling solution in that full refresh rates can be maintained. There are many ways to implement a dual AD9884A design. This application note serves to make the user aware of the considerations that should be weighed when implementing this ping - pong configuration. Among the variables are layout and routing constraints, clock selection, graphics controller requirements, and maximum speed requirements. Analog Input Layout and Routing When laying out and routing the analog inputs (R, G, B, and HSYNC), several factors should be considered. The trace lengths of the R, G, and B inputs should be kept as equal as possible, while also keeping the routes direct (no zig-zagging) to maintain equal propagation delays. The branches to each of the AD9884's analog inputs should be kept as short as possible. The 75 terminators on the
RGB inputs should be placed as close to the branch junctions as possible. Finally, each R, G, and B branch requires its own coupling capacitor. These considerations are illustrated in Figure 1. Clock Source Selection There are three methods that can be used for clocking data. An external clock source can be used to clock both AD9884As as well as data-latching devices (graphics controllers). This method requires ex ternal PLL circuitr y and special high speed clock layout and routing considerations. Another option is to use the PLL in chip 1 to drive chip 2. This method would require chip 2 to be configured for external clock operation, using the negative edge of chip 1's DATACK to sample the RGB data. This method employs the most direct routing of HSYNC. The HSYNC could be routed directly to chip 1, then routed to the second device. (Although the second device does not use HSYNC to generate a clock, it is still needed to provide a timing reference for other functions, such as clamping.) The problem with thi
s option is that it
causes difficulty in setting the correct clock phase of chip 2 because of the added propagation delay between HSYNC and chip 1's data clock output. It can also cause ongoing clock phase difficulty in chip 2 because of the variability of chip 1's data clock propagation delay over time and temperature.
C C C CKINV
AD9884A
L L L
C C HSYNC C 3.3V
AD9884A
CKINV
Figure 1. Analog Input Routing The recommended method for clocking is to use the PLLs in both chips. This method requires special attention to HSYNC input layout, as illustrated in Figure 1. If very careful attention is paid to keeping the branch lengths identical (avoiding zig-zagging), then the skew between the two chips' sampling clock and digital outputs will be negligible. Sampling Clock Inversion All three clocking methods described earlier require chip 2 to sample RGB data 180 out of phase with chip 1. The recommended method for doing this is to use the CKINV input (Pin 27). This method requires that chip 2 have its CKINV input pulled high so that it clocks RGB data using the opposite edge of chip 1. As illustrated in Figure 1, this allows both chips to run their clocks at half of the effective data rate. Chip 1 captures odd data on its sampling edge, while chip 2 captures even data on its sampling edge (180 out of phase from chip 1). An additional benefit of this method is the ability to align the da
ta between the two chips through internal pipeline delay adjustment.
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