81751726ee_47| Application Note
Engineer To Engineer Note
EE-47
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ADSP-2106x Link Ports - Maximum Throughput
Last Modified: 04/23/01
Question: Why can only 4 link ports be sustained if I transmit 32-bit word at LCLK = 80MHz? Answer: 4 transfers are needed to transmit a full 32-bit word at 8bits/cycle. Table1 shows the progression of #bytes left to be sent at each clock cycle for each link port. At clock cycle 1, LP0 starts the transfer and has 4 bytes to send. At cycle 2, LP1 initiates its first byte and LP0 has 3 bytes remaining. By cycle 4, LP0 has transmitted out the entire 32-bit word already but LP4 has not started transmitting yet. There are no more data for LP0 to sustain a continuous transfer. The word size is the limiting factor in the number of link ports that can be continuously sustained. In 32-bit data word transfer at LCLK = 80MHz, only 4 link ports can be sustained.
Cycle 1 2 3 4 3 2 3 4 4 1 2 3 4 5 6
This EE Note will present some benchmarks for Link Port throughput on the ADSP-2106x floating point family DSPs. General benchmark calculations will be shown for 6 dedicated link ports. Also to be discussed is a design that used 3 link ports for transmitting and receiving while other IOP activity is happening at the same time. Three calculations are shown below for maximum sustaining performance through all 6 link ports if no other IOP activity is occurring on the DSP: #1 At LCLK = 40MHz, 4 bits/transfer with all 6 link ports enabled, 32 or 48 bit words: 40MHz * 3bytes/cycle = 120Mbytes/sec sustained. #2 At LCLK = 80MHz (LCLKX2x = 1), the link port can transmit/receive 2x more data for each core clock cycle. With all 6 link ports enabled, 48 bit words: 40MHz * 6bytes/cycle = 240Mbytes/sec sustained. #3 At LCLK = 80MHz, with all 6 link ports enabled, 32 bit words, 4 link ports are always operating at one time for sustained throughput, 2 are always waiting for IOD (I/O Data) service: 40 MHz * 4bytes/cycle = 16
0Mbytes/sec sustained.
LP0 4 LP1 LP2 LP3 LP4 LP5 Table 1
1 2 3 4
1 2
In the case where the word size is 48 bits, 6 transfers are needed to transmit the entire word. Table 2 shows the #bytes left to be transmitted at each clock cycle for all link ports. At cycle 4, LP0 has still 3 bytes to send and LP4 is initiating its first byte. At cycle 6, LP0 finishes sending its 48-bit word while LP5 has already started sending its first byte. Therefore all 6 link ports can be sustained (case #2) in transmission of 48-bit words at LCLK = 80MHz.
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