AD6654_sch| Application Note
6
5
4
E101 VREF R102 DRVDD
1 2
3
1
2
1
1 2
C101 0.1U
1 2
C103 0.1U
FPGA_EC_SEL
10K
1 2
C102 0.1U
MSB_FIRST
EXTFILTER
VDDCORE
TDIODE1
TDIODE0
D
SMODE DTACK MODE AVDD IRP CS
D
DRVDD VDDIO
CHIPID3
CHIPID2
CHIPID1
CHIPID0
RESET
ENC+
TRST
EXP2
EXP1
EXP0
TCLK
ENC-
AIN+
OVR
TMS
AIN-
EC2
R/W
TD0
TDI
DR
DS
VDDIO M16 C11 D11 N11 N10 H16 R16 C12 D12 A13 B11 B12 A12 F16 T16 T14 T12 L16 G1 C2 D3 C3 D2 C4 C1 D1 N9 E2 B4 B2 B3 E1 E4 E3 E6 E9 F1 F4 T8 T9 J1
2
R/W(WR)
AIN+
CHIIPID2
SMODE
MODE
ENC+
AIN-
ENC-
TMS
IRP
RESET
VREF
TCLK
TDO
DRY
NC
AVDD
NC
DRVDD
CHIPID3
CHIPID1
DTACK(RDY)
CHIPID0
DS(RD)
THERMD1
MSB_FIRST
EXTFILTER
THERMD0
EC_SEL
EXPC2
EXPC1
EXPC0
TRST
DVCORE
DVIO
TDI
C2
CS
C1
OVR
DNC
R101 5K Mode Select 1 J101 2
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8
N5 D6 R4 C6 T3 B6 R3 D7 N4 C7 P4 T2 A7 N3 P3 B7 A8 N6 D8 R5 C8 B8 A9 D9 N7 B9
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PAIQ
PA[0:15] (to U301) MODE
A[0:7] A0 A1 A2 A3 A4 A5 K3 J5 K4 L1 K2 K1 H5 J4 J3 F5 G4 H1 H3 G5 J2 B1 G2 G3 H4 H2 A3 F2 A2 F3 T10 R11 P11 T11 A11 A4 T4 A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 SYNC0 SYNC1 SYNC2 SYNC3 CLK CPUCLK PCLK PCGAIN
1
C
D[0:15]
A6 A7 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
C
AD6654
SIGNAL=AGND;L15,M15,N15,N16,P15,P16,R13,R14,R15,T13,T15 SIGNAL=AGND;F15,G15,G16,H15,J15,J16,K15,K16 SIGNAL=AGND;A16,B15,B16,C15,C16,D15,D16,E15,E16 AVDD;H13,H14,J13,J14,K13,K14,L13,L14,M13,M14,N13,N14,P13,P14 AVDD;A14,B13,B14,C13,C14,D13,D14,E13,E14,F13,F14,G13,G14 SIGNAL=VDDCORE;E7,E8,F6,F7,F8,L9,L10,L11,M9,M10,M11 SIGNAL=VDDIO;E10,E11,F9,F10,F11,L6,L7,L8,M6,M7,M8 DRVDD;E12,F12,G12,H12,J12,K12,L12,M12,N12,P12,R12 SIGNAL=GND;J6,J7,J8,J9,J10,J11,K6,K7,K8,K9,K10,K11,T1 SIGNAL=GND;G6,G7,G8,G9,G10,G11,H6,H7,H8,H9,H10,H11
PA9 PA10 PA11 PA12 PA13 PA14 PA15 PAIQ PAREQ PACH0 PACH1 PACH2 PAACK PAGAIN PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PBGAIN
AVDD C104
1 1 2 2
C105
1 2
C106
1 2
C107
1 2
C108
1 2
C109
1 2
C110 0.1U
1 2
C111 0.1U
PAREQ PACH0 PACH1 DRVDD PACH2 PAACK PAGAIN
1 2
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
C112
1 2
C113
1 2
C114
1 2
C115 0.1U
B
D12 D13 D14 D15 SYNC0 SYNC1 SYNC2 SYNC3 CLK CPUCLK PCLK_SRC
0.1U
0.1U
0.1U
B
VDDCORE C120
1 1 2 2
C121
1 2
C122 0.1U
1 2
C123 0.1U
C9 B10 T5 A10 P6 P7 C10 P5 R7 VDDIO
0.1U
0.1U
C128
1 1 2 2
C129
1 2
C130 0.1U
1 2
C131 0.1U
0.1U
0.1U
PCREQ
PBREQ
PB10 DGND PB15 PB14 PB13 PB12 PBIQ PB11
PCACK
PCCH2
PCCH1
PCCH0
PBACK
PBCH2
PBCH1
AGND
PBCH0
PC15
PC14
PC13
PC12
PC11
PC10
PCIQ
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
E5
A6
P2
A15
P1
K5
B5
A5
P9
P8
P10
M5
M1
M2
M3
M4
R2
R1
D4
N2
D5
N1
C5
R8
N8
T7
R9
R10
U101
PCGAIN
PC15
PC14
PC13
PC12
PC11
PCREQ
PCACK
PCCH2
PCCH1
PCCH0
PCIQ
PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
D10
R6
A1
L4
L2
L3
L5
T6
A
A
PLL PC[0:15] 1
TRM 7
6
5
4
3
2
1
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