AN-313| Application Note

DC Electrical Characteristics of MM74HC High-Speed CMOS Logic

DC Electrical Characteristics of MM74HC High-Speed CMOS Logic
The input and output characteristics of the MM74HC high-speed CMOS logic family were conceived to meet several basic goals. These goals are to provide input current and voltage requirements, noise immunity and quiescent power dissipation similar to CD4000 and MM74C metal-gate CMOS logic and output current drives similar to low power Schottky TTL. In addition, to enable merging of TTL and HC-CMOS designs, the MM74HCT sub family differs only in their input voltage requirements, which are the same as TTL, to ease interfacing between logic families. In order to familiarize the user with the MM74HC logic family, its input and output characteristics are discussed in this application note, as well as how these characteristics are affected by various parameters such as power supply voltage and temperature. Also, for those users who have been designing with metal-gate CMOS and TTL logic, notable differences and features of high-speed CMOS are compared to those logic families. A Buffered CMOS Logic Family The MM74HC i
s a "buffered" logic family like the CD4000B series CMOS. Buffering CMOS logic merely denotes designing the IC so that the output is taken from an inverting buffer stage. For example, the internal circuit implementation of a NAND gate would be a simple NAND followed by two inverting stages. An unbuffered gate would be implemented as a single stage. Both are shown in Figure 1. Most MSI logic devices are inherently buffered because they are inherently multi-stage circuits. Gates and similar small circuits yield the greatest improvement in performance by buffering.

Fairchild Semiconductor Application Note 313 Larry Wakeman April 1998

There are several advantages to buffering this high-speed CMOS family. By using a standardized buffer, the output characteristics for all devices are more easily made identical. Multi-stage gates will have better noise immunity due to the higher gain caused by having several stages from input to output. Also, the output impedance of an unbuffered gate may change with input logic level voltage and input logic combination, whereas buffered outputs are unaffected by input conditions. Finally, single stage gates implemented in MM74HC CMOS would require large transistors due to the large output drive requirements. These large devices would have a large input capacitance associated with them. This would affect the speed of circuits driving into an unbuffered gate, especially when driving large fanouts. Buffered gates have small input transistors and correspondingly small input capacitance. One may think that a major disadvantage of buffered circuits would be speed loss. It would seem that a two or three stage gate
would be two to three times slower than a buffered one. However, internal stages are much faster than the output stage and the speed lost by buffering is relatively small. The one exception to buffering is the MM74HCU04 hex inverter which is unbuffered to enable its use in various linear and crystal oscillator applications.

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(a) (b) FIGURE 1. Schematic Diagrams of (a) Unbuffered and (b) Buffered NAND Gate CMOS Input Voltage Characteristics As mentioned before, MM74HC standard input levels are similar to metal-gate CMOS. This enables the high-speed logic family to enjoy the same wide noise margin of CD4000 and MM74C logic. With VCC = 5V these input levels are 3.5V for minimum logic "1" (VIH) and 1.0V for a logic "0" (VIL). The output levels when operated at VCC = 5V 10% and worst case input levels, are specified to be VCC-0.1 or 0.1V. The output levels will actually be within a few millivolts of either VCC or ground.

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When operated over the entire supply voltage range, the input logic levels are: VIH = 0.7VCC and VIL = 0.2VCC. Figure 2 illustrates the input voltage levels and the noise margin of these circuits over the power supply range. The shaded area indicates the noise margin which is the difference between the input and output logic levels. The logic "1" noise margin is 29% of VCC and the logic "0" noise margin is 19% of VCC. Also shown for comparison are the 74LS input levels and noise margins over their supply range.

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1998 Fairchild Semiconductor Corporation

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