AN-375| Application Note

High-Speed-CMOS designs address noise and I/O levels

High-Speed-CMOS designs address noise and I/O levels
Designs using high-speed-CMOS logic, such as the MM54HC/74HC Series, can attain characteristics that mark improvements over LS-TTL designs. To optimize these characteristics, however, you must adopt proper design procedures. This article deals with the ICs' input-output and noise-immunity considerations. High-speed CMOS logic is essentially a digital-IC family that combines TTL (bipolar) and CD4000 (CMOS) characteristics. Because of the family's high speed, you must be more aware of the requirements of fast systems than in the case of CD4000B logic. Although the 54HC/74HC IC's CMOS construction results in noise immunity comparable to the CD4000 family, its high speed necessitates system-grounding and supply-decoding techniques normally used in LS-TTL system design. The following sections discuss general usage guidelines, system noise susceptibility and immunity, and the 54HC/ 74HC logic's power-supply-noise characteristics. Note that, unless specific exceptions are stated, the considerations discussed apply
also to 54HCT/74HCT, HC's TTL-compatible subset. FOLLOW BASIC GUIDELINES The basic rules for designing with 54HC/74HC circuits are similar to those that apply to 74LS, CD4000B and 54C/74C devices. First, under normal static operating conditions, the

Fairchild Semiconductor Application Note 375 October 1984

To maximize the benefits of high-speed CMOS, you must cope with environmental interactions and component limitations. Especially important are system noise decoupling and both transient and steady-state level control.
input should not exceed VCC or go below ground. In normal high-speed systems, transients and line ringing can cause inputs to violate this rule momentarily, forcing the ICs to enter an SCR-latch-up mode. Latch-up results if either the input- or output-protection diodes are forward biased because of voltages above VCC or below ground. As a result, the IC's internal parasitic SCR shorts VCC to ground Figure 1 shows the diodes in a CMOS IC, schematically (a) and in a simplified die cross section (b). Thanks to some processing refinements, SCR latch-up isn't a problem with the MM54HC/74HC Series. There are, however, limitations on the currents that the internal metallization and protection diodes can handle, so for high-level transients (pulse widths less than 20 ms and inputs above VCC or below ground), you must limit the current of the IC's internal diode to 20 mA rms, 100 mA peak. Usually, a simple resistor configured in series with the input suffices.

AN-375

1998 Fairchild Semiconductor Corporation

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