AN-42032| Application Note
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Application Note 42032
FAN4822 Power Factor Correction With Zero Voltage Resonant Switching
Introduction
The boost converter is a popular topology for improved power factor and reduced line harmonics, as specified in IEC 555-2 and other more recent standards. With this solution limitations inherent in the continuous conduction mode (CCM) boost converter topology have been recognized. As with all power converters, limitations on operating frequency are always of interest. Higher operating frequencies allow for smaller filter components both at the output and input filter. This reduces cost and increases packaging density. The fundamental limitations on the operating frequency of the CCM boost converter are the reverse recovery current associated with the boost diode and the switching losses associated with the FET output capacitance. At frequencies above 100kHz these losses become excessive. A typical method for reducing reverse recovery currents is the addition of L2 in series with the main switching transistor (see Figure 1). Inductor L2 requires an equivalent voltseconds during the off time for proper reset.
This method requires a tapped boost inductor to provide the extra voltage required for reset. Also, L2 must carry the same current seen by the main FET. Although this method does provide significantly reduced reverse recovery currents it does not eliminate the switching losses associated with the capacitance at the drain node being discharged by the FET.
L1 D1 VAC Rectified
L2 D2 D3 Q1 + C1 VAC Rectified Return
Figure 1. Tapped Boost
VEAO FB 14 2.5V IAC 4 VRMS 5 ISENSE 3 RTCT 6 VEA
1
8
GND
2
IEAO VCC OVP
+
R+
FB
+ -
VCC 13.5V
12
+ -
IEA
2.7V
+ R-1V I LIMIT S Q
+ -
R
Q PFC OUT 11
OSC VCC REF
S
Q ZVS OUT
R REF S
Q
10
13
Q PWR GND
ZV SENSE 7
+
R
Q
-
9
Figure 2. Block Diagram
REV. 1.0.2 10/10/01
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