AN-57| Application Note

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Application Note 57
Third Generation Power Conversion Solution for Pentium II Motherboards
Abstract
This application note provides detailed design procedures for the development of the Core supply for Intel Pentium II and beyond motherboards using Fairchild Semiconductor's third generation controller RC5052/RC5057 both of which were designed to meet the Intel VRM8.4 specification.

DC Voltage Regulation
The voltage level supplied to the CPU must be within +50mV and 80mVof its nominal setting (VRM8.4). Voltage regulation limits must include: Output load range Output ripple/noise DC output initial voltage set point Temperature and warm up drift (Ambient +0 C to +70 C at full load with a maximum rate of change of 5 C per 10 minutes but no more than 10 C per hour) Output load transient with: Slew rate >20A/us at converter pins Range: 0.3A - ICCP Max.

Introduction
As the demand for tighter tolerance increases coupled with the need for less component count and higher performance, the RC5052 and RC5057 PWM controllers were designed to fulfill that demand. The PWM controller implements robust yet flexible voltage-mode and current-mode control architecture which eliminates that need for external compensation. Provides 1% accurate reference and over current protection employing MOSFET RDS(ON) . Both RC5052 and RC5057 are designed to fully meet Intel's VRM8.4 Specifications. RC5052 comes in a 20 lead SOIC package and sports fully featured control of the major parameters while RC5057 comes in a 16 lead SOIC package with pre-selected key parameters like switching frequency and gate drive dead time. The step down DCDC converter can deliver up to 18A of continuous load current at voltages ranging from 1.3V to 3.5V. A specific application circuit, design considerations, component selection, PCB layout guidelines, and performance evaluations are covered in detail.

Output Ripple and Noise
Ripple and noise are defined as periodic or random signals over the frequency band of 0 - 20MHz at the output pins. Output ripple and noise must be consistent with voltage requirements throughout the full load range and under all specified input voltage conditions.

Efficiency
The efficiency of the DC-DC converter must be greater than 80% at maximum output current and greater than 40% at low current draw.

Intel Pentium II Processor Power Requirements
Refer to Intel's AP-587 Application Note, Slot 1 Processor Power Distribution Guidelines, May 1997 (order number 243332-001 ), as a basic reference. Available inputs are +12V+5% and +5V+5%. The input voltage requirements for Fairchild's RC5052/RC5057 DC-DC converter are listed in Table 1. See below for detailed information on how to apply these.

Processor Voltage Identification
There are five Voltage Identification Pins, VID0-VID4, on the Pentium II processor package which can be used to support automatic selection of the power supply voltage. These pins are either internally unconnected or are shorted to ground (VSS). The logic status of the VID pins defines the voltage required by the processor.

I/O Controls
In addition to the Voltage Identification, there is a signal that provides feedback from the DC-DC converter to the CPU. This is the Power-Good (PWRGD) signal, which will be discussed later. Rev. 1.0

Table 1. Input Voltage Requirements
Part # RC5052/ RC5057 Vcc for IC +5V +5% +12V +5% MOSFET Drain +5V +5% or 12V +5% For switching Converter

Pentium is a registered trademark of Intel Corporation.