AN-7515| Application Note
A Combined Single Pulse and Repetitive UIS Rating System
Application Note March 2002 AN-7515 (AN9322)
/Title AN75 5) ubct (A omned ngle The ability of PowerMOS transistors to withstand unclamped inductive switching (UIS) has been recognized since 1985. ulse Although Blackburn has clearly shown [1] UIS stress level is nd not directly related to energy, many manufacturers of epeti- PowerMOS transistors persist in rating their devices in terms of energy capability. Since the energy capability varies with ve the operating conditions, this rating is valid only at the IS ating condition specified and the PowerMOS transistor user has no way to calculate whether the particular application ysexceeds the device rating. Ronan has defined a rating m) system [3], herein after called simply the UIS Rating System, Autho which allows manufacturers to specify the capability of their PowerMOS transistors for single pulse UIS in such a way () that users can easily determine if their application exposes Keyords the device to more UIS stress than is guaranteed in the device data sheet. nterl The Single Pulse UIS Rating System or
po- This UIS Rating System, requires the user to determine only tion, the peak current through the PowerMOS transistor (IAS), the emi- junction temperature at the start of the UIS pulse (TJ) and the time the transistor remains in avalanche (tAV). It allows onuctor, the easy determination of the conformance of any omned ngle ulse nd epetive IS ating ysm)
application to a specified UIS capability where the worst case conditions can be simulated. It is also quite feasible to calculate the UIS stresses for circuits not yet constructed or conditions not easily simulated.
A rating system for Unclamped Inductive Switching in PowerMOS transistors already widely accepted and implemented on Fairchild PowerMOS transistor data sheets can be applied to a wide range of applications very easily and expanded to cover repetitive UIS pulses by the simple technique of superposition. This allows PowerMOS transistor users to determine if their application lies within the rated capability of a power transistor. Two examples are given of the analysis of UIS stress level in representative applications.
analysis is needed. If the time and current plotted on the rating chart falls between the 25oC and the maximum junction temperature lines further analysis is required. To analyze those cases where the starting temperature and time in avalanche fall between the 25oC and maximum temperature line, first we must determine the junction temperature of the PowerMOS transistor at the start of the UIS pulse. If the UIS stress occurs after a long period in conduction it may be sufficient to just measure the case temperature of the device and calculate the temperature rise between the case and junction from the dissipation and thermal resistance of the device. Any other approach may be used. Once the junction temperature at the start of the pulse has been determined we can extrapolate between the two published rating curves to determine the UIS capability at that starting junction temperature. Ronan [3], Stoltenburg [2] and Blackburn [1] have all indicated that the UIS capability I2AS xtAV is a simple linear function o
f temperature. Using this allows a straight line extrapolation of the UIS capability of the device at the calculated junction temperature. Then simply compare the calculated capability to the stress determined to determine if the device is within ratings. This simple approach allows users to find out if their application is safe for any single UIS pulse.
300 IDN 100 IAS (A) IF R = 0 tAV = (L)(lAS)/(1.3 RATED BVDSS - VDD) IF R 0 tAV = (L/R) ln[(IASxR)/(1.3 RATED BVDSS - VDD) + 1]
STARTING TJ = 25oC STARTING TJ = 150oC
RFP70N06 10 0.01 0.10 1.00 tAV, TIME IN AVALANCHE (ms) 10.00
The UIS rating for a PowerMOS transistor (see Figure 1) is presented as a chart with a vertical axis of (IAS) maximum avalanche current vs (tAV) time in avalanche as the horizontal axis. Two lines are shown, one for 25oC and one for the maximum junction temperature. It is fairly easy in most applications to determine the avalanche current and time in avalanche in an existing application by using a current probe. If the time in avalanche and avalanche current plotted on the UIS rating curve fall above and to the right of the 25oC line, the application is beyond the UIS rating of the device and the user stands a risk of device failure. If the time and current plotted on the rating curve fall below and to the left of the maximum junction temperature line the application is within the UIS rating of the device. In either case no further
2002 Fairchild Semiconductor Corporation
FIGURE 1. UNCLAMPED-INDUCTIVE-SWITCHING (SINGLE PULSE UIS)
Multiple or Repetitive UIS
The handling of repetitive UIS pulses has been ignored by the PowerMOS transistor manufacturers except for an attempt by one manufacturer to rate repetitive UIS at 0.01% of the 25oC power rating with no further qualifications. The UIS rating system outlined in Ronan's paper [3] is quite applicable to repetitive pulses by using the technique of superposition as is commonly done in evaluating repetitive SOA pulses. Each UIS pulse is considered a separate event
Application Note 7515 Rev. A2
AN-7515 Application Note fairchild Download PDF
Add this permalink to your bookmarks for future download of AN-7515 ApplicationNote
Permalink: http://application.emcelettronica.com/fairchild/AN-7515
