MS-569| Application Note

Section 9- Layout Considerations Backplane Designer's Guide

March 2002 Revised April 2002

Section 9- Layout Considerations Backplane Designer's Guide
The best backplane designs allow the components to operate at peak efficiency. Minimizing compromises and enhancing all design parameters enable backplanes to do more with less. To increase efficiency, for example, the I/O technology chosen should allow the backplane to run at maximum frequency. This is achieved by minimizing impedance discontinuities and noise and by carefully matching termination design. The alternative to optimizing I/O technology is selection of higher drive and speed technology and operation at slower than optimum speeds. The first method choice of the correct I/O technology reduces overall cost and delivers better signal integrity than the second "brute force" method. An optimized backplane will use less power, generate little noise, have better signal integrity, and be less costly. For this reason, it is key for the designer to understand how the components interact with each other when laying out a backplane.

Section Reference
This section addresses layout considerations for a backplane design with primary focus on optimizing the overall design. It discusses: Performance Trace Layout and Vias Clock and Signal Routing Skin Effect Shielding Board Layout Board Materials Section 1 2 3 Section Title Introduction Backplane Protocols Backplane Architecture Contents Application demands, basic backplane considerations, and how to use this guide. Descriptions of different backplane bus protocols, including PCI- and VME-based protocols. Topics relevant to backplane configuration, including parallel versus serial configuration and different configuration topologies and timing architectures Issues relevant to backplane layout, including distributed capacitance, transmission line effect, stub length, termination, and throughput. Signal driving and conditioning, including power consumption, rise/fall time, propagation delay, flight time, device drive, pin conditioning, live insertion, and incident wave switching. A review of the en
emies of signal integrity and high frequency. Detailed information about the following technologies: TTL-based (ABT, FCT, and LVT); ECL; and GTLP. Information about mechanical considerations such as backplane chassis/cages and connectors. Physical layout of the receiver and driver cards plugged into the backplane, primarily focusing on construction of the physical layer and the configuration of the devices that comprise the cards.

Backplane Design Considerations Backplane Signal Driving and Conditioning Noise, Cross-talk, Jitter, Skew and EMI Transceiver Technologies Mechanical Considerations

5 6 7 8

Layout Considerations

2002 Fairchild Semiconductor Corporation

MS500739

www.fairchildsemi.com