ispsd01flipchip| Application Note
Flip Chip Power MOSFET: A New Wafer Scale Packaging Technique
Aram Arzumanyan, Ritu Sodhi, Dan Kinzer, Hazel Schofield, Tim Sammon International Rectifier Corporation, El Segundo, CA 90245 USA As presented at ISPSD, June 2001
Abstract This paper describes the first flip chip power MOSFET device with the lowest R DSON per footprint area in the industry. This device, with the same electrical characteristics as an SO8 packaged device, takes only 30% of the SO8 footprint. RSi x Footprint Area as low as 59 mOhm.mm2 were achieved for bi-directional device and 98 mOhm.mm2 for single device at 4.5 VGS, a 4-6 times reduction compared to regular packaged MOSFET. The typical applications for these parts include battery charging and load switching in cell phones and laptops. Introduction In the last few years the power MOSFET industry has continuously improved RDSON per footprint value. Cell phone and other portable device manufacturers are in constant search for smaller, lighter and lower profile devices. To address this demand, power MOSFET designers implemented the trench technology, which utilizes the body of the silicon die in addition to the surface by densely packing vertical channels instead of planar surface channels. This decreased
the chip size significantly for given RDSON. However, any type of conventional package always adds to the size of the silicon die in all 3 dimensions - length, width and height. At best, the silicon die still counts only one third of the package footprint. Hence, it becomes very critical that new packaging technologies be developed to take full advantage of the silicon performance. In this paper, we present the first flip chip power MOSFETs. This emerging wafer scale packaging technique brings the size of a device to it's bare minimum to the size of the silicon die. Our flip chip power MOSFET design brings all terminals of MOSFET on top of the die. This is followed by solder balls formation for the three electrodes. Users then flip the die over the circuit board and melt the solder to mount the device for their application. Figure 1 shows the SEM picture of a typical flip chip power MOSFET. Figure 1. SEM picture of a flip chip power MOSFET Device Design and Process Description A. Single Flip Chip Power MO
SFET In a vertical power MOSFET, the drain electrode is on the back of the die. The challenge for making a vertical flip chip power MOSFET is to bring the drain electrode to the front of the die, together with the source and gate electrodes. This design is based on International Rectifier's low voltage, ultra-low RDSON, cellular trench technology. This very high channel density design has been successfully used in numerous p-channel and n-channel extremely low RDSON benchmark products. The design layout has one gate, one source, and two drain electrodes on the front of the die. The gate electrode is contacted to the polysilicon mesh inside the trench through the gate bus, which travels around the perimeter of the device and between two drain electrode stripes. The source electrode is contacted to the source regions of all cells in active area through top metal layer. The drain electrode consists of two stripes, and is connected to the low resistivity substrate through deep diffusion of substrate type dopant,
such as Boron for pchannel device. The size of the drain region is optimized to collect all drain current from the top of the die with the
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