pee02directfet| Application Note
DirectFET TM Technology: A Mechanically robust Surface Mount Technology
Stuart Cardwell & Andrew Sawle International Rectifier, Holland Road, Hurst Green, Oxted, Surrey, RH8 9BB, UK As presented at the Power Electronics Conference, May 2002
Abstract This paper outlines a selection of mechanical TM tests performed on the DirectFET package, It details the reasoning behind the initiative and presents some of the results obtained. 1. Introduction The evolution of faster and more powerful processors is driving ICs to lower operating voltages and higher current requirements; simultaneously space requirements are getting tighter. This demand for higher power/current densities puts even greater emphasis on the need to reduce the size, and electrical and thermal resistance of the associated semiconductor devices delivering this power. Up to now many of the power semiconductor devices have been incorporated into IC type packaging such as the SO8 package. However it is becoming increasingly difficult to meet the thermal, electrical and geometrical needs with these package outlines (see Figure 1a).
Rth (j-c): 25 C/W
It is source mounted and incorporates a copper can as the drain contact on the back to allow for backside (dual-side) cooling (see Figure 1c). Due to these innovations, the die-free-package resistance has been reduced from 1.5m for a TM standard SO8 to 0.1m for the DirectFET package, with the Junction to Board thermal resistance having been reduced from 20 0C/W for a Standard SO8 to 10C/W for the DirectFETTM Package, and the junction to top of package 0 thermal resistance down from 25 C/W for a 0 TM Standard SO8 to only 1 C/W for the DirectFET package (see Figures 1a and 1b).
Passivated die Copper `drain' clip Die attach material
Gate connection Copper track on board Rth (j-b): ~20 C/W An (SO8) showing the main thermal resistances. Fig. 1c
Source connection
SO8 Fig. 1a
Cross-section of a DirectFETTM showing large die to footprint ratio
Some innovations such as the Copper Strap SO8 and MLPs (Micro Lead Packages) have been able to help the situation somewhat but still the requirements increase.
Rth (j-c): 3 C/W
Rth (j-b): 1 C/W DirectFETTM TM Fig. 1b A DirectFETTM Mosfet device showing the main thermal resistances
TM
The DirectFET package technology was designed from a clean sheet to accommodate these demands. This innovative design allows for a greater die to footprint ratio and reduced thermal and electrical resistance [1].
Surface mount technology is used in many of the new IC and Power Device packages, changing the attachment to the PCB from being purely electrical to electrical-mechanical. This attribute is often overlooked when subjecting the devices to reliability tests. With this in mind it was decided to subject it to a selection of suitable mechanical tests. These were to include bending, which could simulate stresses induced from the printed circuit board during board assembly, compression which would give maximum force values for the attachment of heat sinks or other similar heat exchangers to the back of the component, vibration which could approximate long term vibrations induced during the working life of the component, and shock or drop tests which simulate the extreme accelerations components on boards undergo during such situations.
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