AN1080| Application Note
Maxim > App Notes > A/D and D/A CONVERSION/SAMPLING CIRCUITS Keywords: sar, successive approximation, adc, analog to digital, converter, precision
Mar 01, 2001
APPLICATION NOTE 1080
Understanding SAR ADCs
Abstract: Successive-approximation-register (SAR) analog-to-digital converters (ADCs) represent the majority of the ADC market for medium to high resolution ADCs. SAR ADCs provide up to 5Msps sampling rates with resolutions from 8 to 18 bits. The SAR architecture allows for high performance, low power ADCs to be packaged in small form factors for today's demanding applications. This paper will explain how the SAR ADC operates using a binary search algorithm to converge on the input signal. It also provides an explanation for the heart of the SAR ADC, the capacitive DAC and also the highspeed comparator. Finally, the article will contrast the SAR architecture against pipeline, flash ADCs. Successive-approximation-register (SAR) analog-to-digital converters (ADCs) are frequently the architecture of choice for medium-to-high-resolution applications with sample rates under 5 megasamples per second (Msps). SAR ADCs most commonly range in resolution from 8 to 16 bits and provide low power consumption as well as a
small form factor. This combination makes them ideal for a wide variety of applications, such as portable/batterypowered instruments, pen digitizers, industrial controls, and data/signal acquisition. As the name implies, the SAR ADC basically implements a binary search algorithm. Therefore, while the internal circuitry may be running at several megahertz (MHz), the ADC sample rate is a fraction of that number due to the successive-approximation algorithm.
SAR ADC Architecture
Although there are many variations in the implementation of a SAR ADC, the basic architecture is quite simple (see Figure 1). The analog input voltage (VIN) is held on a track/hold. To implement the binary search algorithm, the N-bit register is first set to midscale (that is, 100... .00, where the MSB is set to '1'). This forces the DAC output (VDAC) to be VREF/2, where VREF is the reference voltage provided to the ADC. A comparison is then performed to determine if VIN is less than or greater than VDAC. If VIN is greater than VDAC, the comparator output is a logic high or '1' and the MSB of the N-bit register remains at '1'. Conversely, if VIN is less than VDAC, the comparator output is a logic low and the MSB of the register is cleared to logic '0'. The SAR control logic then moves to the next bit down, forces that bit high, and does another comparison. The sequence continues all the way down to the LSB. Once this is done, the conversion is complete, and the N-bit digital word is available in the register
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