AN3347| Application Note
Maxim/Dallas > App Notes > TELECOM Keywords: HDLC Controller, T3, E3, HSSI, VDSL, Unchannelized Port
Sep 09, 2004
APPLICATION NOTE 3347
DS31256 Unchannelized T3/E3/HSSI/VDSL Port Configuration for Bridge Mode Applications
This application note provides an example of how to configure a single T3/E3/HSSI/VDSL port for unchannelized operation on the DS31256 in bridge mode. It includes a coding example for easy adaptation to end-user applications.
Overview
This application note describes an example of how to configure a single T3 port for unchannelized operation on the DS31256 in bridge mode. Additionally, this example describes how to construct, send, receive, and check a packet in loopback mode on that port. This application note is presented as a coding example for easy adaptation to end-user applications. The DS31256 local bus can operate in two modes : 1. PCI Bridge Mode 2. Configuration Mode The PCI bridge mode allows the host on the PCI bus to access the local bus. The PCI bus is used to control and monitor the DS31256 and transport packet data in this application. The DS31256 also is configured to map data from the PCI bus to the local bus for control and monitoring of peripheral components such as xDSL modems or T3/E3 interfaces. This example has the following configuration:
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Port 1 of the DS31256 is operated as an unchannelized port. That is, the port gets receive/transmit clocks but no sync pulse. All other ports are not used. HDLC channel 0 is assigned to port 1 of the DS31256. It also is assigned 256 RX FIFO blocks, 256 TX FIFO blocks, an RX FIFO high watermark of 179 (70% of 256), and a TX low watermark of 77 (30% of 256). Ten 16-byte packets are constructed in host memory using 10 TX buffers, 10 TX descriptors, and one TX pending-queue entry. The TX pending-queue entry points to a descriptor, which is chained to 10 descriptors via the next-descriptor pointer-field and the EOF and CV being set. Since the DS31256 is in loopback mode, the packet, when transmitted, also will be received by the DS31256. The received packet is written to host memory using 10 RX buffers, 10 RX descriptors, and 10 RX done-queue entries. The host memory is configured as follows: Receive Side RX free queue base address (RFQBA1/0) = 0x10000000 RX done queue base address (RDQBA1/0) = 0x10000B00 RX desc
riptor base address (RDBA1/0) = 0x10001080 RX buffer base address = 0x10002680 Transmit Side TX pending queue base address (TPQBA1/0) = 0x10059084 TX done queue base address (TDQBA1/0) = 0x10059604 TX descriptor base address (TDBA1/0) = 0x10059B84 TX buffer base address = 0x1005B184
Definition Of The Coding Example Function Calls
To improve readability, the code in this example uses several function calls. The definitions of these functions are as follows:
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write_reg(address, data) Write the specified data to the specified DS31256 register address Inputs: address = the register address where data is to be written data = the data to be written to the specified register Outputs : None read_reg(address, data) Read the contents of the DS31256 register at the specified address Inputs: address = the register address which is to be read Outputs:
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