AN3479| Application Note

Maxim/Dallas > App Notes > TELECOM Keywords: DS2154, timing, TS0, framing, TSYNC, TCLK, E1, single chip transceiver, SCT, app note 3479

Feb 23, 2005

APPLICATION NOTE 3479

DS2154 Migrating from Revision A2 to D1
This application note describes the procedures for replacing the A2 revision of the DS2154 with the D1 revision of the DS2154. The D1 revision of the DS2154 is a drop-in replacement for the A2 revision of the DS2154. However, it is possible that the user may experience a timing-related issue while replacing the parts. This application note will describe what to do to correct this problem.

Differences Between the Revisions
The DS2154 revision A2 is manufactured using a 0.8um CMOS process. The DS2154 revision D1 is manufactured using a 0.6um CMOS process. For both the A2 and D1 revision of the DS2154, the registers are in a random state on power-up. The user must program all the internal registers to a known state before proper operation can be ensured. This includes setting the test registers to 00h. The most efficient way to perform this initialization is to use a routine to write 0x00 from address 0x00 to 0xFF.

Transmit-Side Timing Diagrams
For reference, the transmit-side timings between TSYNC and frame number, TSYNC and time slot number, and TSYNC and TCLK are shown in the following figures. Note that they are the same for both the A2 and D1 revisions. (Please refer to the DS2154 data sheet for further details.)

Figure 1. Transmit-side timing between TSYNC and frame number.

Figure 2. Transmit-side timing between TSYNC and time slot (TS) number.