AN3890| Application Note
Maxim/Dallas > App Notes > COMMUNICATIONS CIRCUITS
HIGH-SPEED INTERCONNECT
Keywords: DS28CZ04, HFRD, active copper, SFD, cable, gigabit ethernet, infiniband, GBIC, Small Form-factor Pluggable, tranceiver, MSA, fibre, channel, serial, ID, MAX3982, MAX3748A
Aug 02, 2006
APPLICATION NOTE 3890
Using the DS28CZ04 in an Active Copper SFP Cable Assembly
This document is a supplement to the HFRD-16.0 reference design, 1Gbps to 4.25Gbps Active Copper SFP Cable Assembly. It shows how to use the DS28CZ04 as an SFP serial-control interface in active copper SFP cable assemblies. The reader is advised to obtain a copy of the reference design to understand details beyond the scope of this document.
Introduction
Network switches for Fibre-channel, Gigabit Ethernet, and InfiniBand operate at data transfer rates of 1Gbps and above. The standard interface for such equipment is the SFP port (small form-factor pluggable), which provides the same functionality as a regular GBIC (gigabit interface converter) but in a smaller and denser physical size. Active copper SFP cable assemblies plug directly into the SFP ports. Transceiver electronics built into the connector of such cables regenerates and conditions the signal for up to 20 meters in length between devices at 4.25Gbps. The Small Form-factor Pluggable (SFP) Transceiver MultiSource Agreement (MSA)1 defines the mechanical (physical dimensions) and electrical interface (pin assignment, protocol, etc.), including specification of the module definition interface and the data field descriptions. These plug-and-play data fields, also referred to as SFP Serial ID, are stored in an I2C bus CMOS EEPROM device. The DS28CZ042 4kb I2C/SMBus EEPROM meets the SFP requirements. Its
general-purpose I/O ports provide additional functionality to control a MAX3982 copper cable preemphasis driver or to report the state of the incoming signal at a MAX3748A receiver through the serial interface.
Circuit
Figure 1 shows the simplified schematic of the circuit used at either end of the cable. The box at the top left section represents the SFP connector with all signals and pin assignment. A cross reference between pin name and signal function is found in Table 1. The DS28CZ04 I2C memory chip connects to MOD-DEF1, MOD-DEF2, and transmitter power/ground. To reside on the correct SFP slave address, the address pins A1 and A2 need to be tied to ground. Write protect (WP) and master reset (MRZ) are not used; these pins are tied to ground (WP) and power (MRZ), respectively. PIO2 and PIO3 control the preemphasis inputs of U2, the MAX39823 driver chip. The transmit data is routed AC-coupled from the SFP connector to the differential inputs of U2. The differential outputs directly drive the cable. The amplitude of the differential output can be set to one of two levels through the OUTLEV input, which is controlled by PIO1. For further information on how the remaining pins of U2 are connected, see the HFRD-16.0 document
cited above. In the schematic the output of the MAX3982 driver chip is controlled through the TX Disable signal coming from the SFP connector. This is one way to prevent activity at the differential output in case there is no data to be transmitted. Alternatively, one can ignore the external TX Disable signal and instead have the MAX3982 disable its output if it cannot detect data at its differential inputs. In this case, one connects the LOS output of the MAX3982 directly to the TX_DISABLE input of the MAX3982. The TX_DISABLE of the MAX3982 has an internal pull-up resistor. A third method combines automatic with controlled TX_DISABLE. This approach requires an additional 2 input OR gate with one of the inputs tied to TX Disable at the SFP connector and the other tied to pull-up resistor to VCCT. The output of the OR gate then drives the MAX3982 LOS output, which requires a 10k the TX_DISABLE input of the MAX3982.
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