AN3901| Application Note
Maxim/Dallas > App Notes > A/D and D/A CONVERSION/SAMPLING CIRCUITS INFRASTRUCTURE COMMUNICATIONS CIRCUITS
BASESTATIONS / WIRELESS
Keywords: synchronizing, high-speed, multiplexing, DAC, digital to analog, transmit, transmitter applications, quadrature modulator, I and Q, beam forming, clock divider, double data rate, DDR, quad data rate, QDR, phase detector, PFD, swallowing clock pulses
Aug 17, 2006
APPLICATION NOTE 3901
Synchronizing Multiple High-Speed Multiplexed DACs for Transmit Applications
This application note proposes methods for synchronization of multiple high-speed digital-to-analog converters (DACs) with multiplexed inputs or integrated interpolation filters. Such DACs are used in I/Q upconverters or digital beam-forming transmitters. These DACs provide a data-clock output for synchronization with the data source.
Introduction
Multiple analog outputs with accurately known relative phase must be generated in many transmit applications. In a quadrature modulator (Figure 1), the I and Q channels must have a well-defined phase relationship to achieve image rejection. In Figure 1, the delays of DAC1 and DAC2 must be well matched. Transmitters using digital beam forming might need accurate control of the relative phase of a large number of DACs.
Figure 1. DACs and first upconversion stage of an I/Q transmitter using MUX-DACs. When using a DAC with multiplexed inputs (MUX-DACs), such as the MAX19692, or an interpolating DAC with a data clock output, the input data rate is 1/N times the DAC update rate, and the DAC is latching data on one or both data clock transitions. In the MAX19692, N = 4, and the input data rate is one-fourth the DAC update rate. The DAC outputs a data clock (DATACLK) that is derived from the input clock with a digital clock divider. When the DAC is powered up, the digital clock divider can start up in any one of N states. If multiple DACs are used, the clock dividers of different DACs may start up in different states; hence, the DACs will latch data at different times. Unless this is detected and corrected, different DACs may output data delayed by one or more clock cycles with respect to each other. If the clock divider in each DAC can be reset, this condition can be avoided, but there are some problems with this solution. If a
n error occurs in one of the clock dividers, the DACs become permanently out of phase unless some means of detecting the error condition is implemented. In order to ensure a robust system, it is necessary to detect a phase-error condition and correct for it. If the DAC is operating at very high speed, it may also be challenging to synchronize the reset signal to the input clock.
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