AN4058| Application Note
Maxim > App Notes > AUTOMOTIVE
HIGH-SPEED INTERCONNECT
Keywords: skew, margin, RSKM, receiver, deserializer, LVDS, interconnect, strobe signal, inter-symbol interference, ISI, jitter, data, clock, misalignment
May 31, 2007
APPLICATION NOTE 4058
Measuring Skew Margin on 4-Channel Deserializers
Abstract: The skew margin of an LVDS deserializer is an indication of its jitter tolerance. This application note describes conditions that can limit skew margin, and it presents a procedure for measuring skew margin on 4-channel deserializers.
Introduction
The skew margin of an LVDS deserializer is an indication of its jitter tolerance. Application Note 3821: Skew Margin Measurement for 4-Channel (3 Data Channels Plus Clock Channel) LVDS Serializers/Deserializers demonstrates an approach for measuring skew margin by utilizing a serializer and LVDS interconnect. This application note describes how to measure skew margin utilizing only a deserializer. The outlined procedure can be used for virtually any LVDS deserializer.
Receiver Skew Margin (RSKM)
RSKM is a valid timing window in which a deserializer can correctly sample LVDS input data. To sample the data within the data-bit time (unit interval or UI), a timing strobe signal is generated from the LVDS input clock. Ideally, this strobe signal should be positioned in the middle of the data pulse, so the maximum RSKM can approach half of the LVDS data bit. However, many nonideal, internal and external conditions can reduce the available timing margin to the point where the sampling window closes and data "errors" develop. Some of the internal chipset parameters that can limit RSKM are listed below: 1. Deserializer internal strobe uncertainty, which is related to data setup and hold timing requirements 2. Transmitter pulse position variation, which is the change in the position of individual serializer output data bits with respect to the serializer LVDS clock Other RSKM-reducing factors are related to LVDS interconnect and include: 1. Cable skew 2. Intersymbol interference (ISI) 3. Parallel input-clock
jitter passed by the serializer to the deserializer
Improving RSKM
The main factors contributing to cable skew are cable length, cable type, and cable quality. The following design recommendations can be implemented to improve RSKM: 1. Use short, high-quality cables with a low skew per unit length (10 20ps/ft). Note that the total skew path also includes the connector and PCB trace skew. Good quality connectors and good board layout practices (e.g. matched trace lengths) add little or no skew. 2. The use of short cables, DC-balanced mode, and a line equalizer minimize the effect of ISI. 3. Applying a clean input-clock signal to the serializer improves the jitter performance of the data/clock and maintains a good skew margin. Also, proper transmission line termination prevents reflections and assists in maintaining signal integrity and skew margin.
Recommended Equipment
AgilentTM 8133A pulse generator Tektronix CSA8000 or similar digital sampling scopes Tektronix P6248 differential probe Tektronix 1103 TEKPROBE BNCTM power supply SMA cables
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