AN476| Application Note
Maxim > App Notes > BATTERY MANAGEMENT
POWER-SUPPLY CIRCUITS
Keywords: I2C, SMB, serial interface, i2c bus, 2-wire buses, smbus
Dec 01, 2000
APPLICATION NOTE 476
Comparing the I2C Bus to the SMBus
Abstract: The I2C bus and the SMBus are popular 2-wire buses that are essentially compatible with each other. Normally devices, both masters and slaves, are freely interchangeable between both buses. Both buses feature addressable slaves (although specific address allocations can vary between the two). The buses operate at the same speed, up to 100kHz, but the I2C bus has both 400kHz and 2MHz versions. Complete compatibility between both buses is ensured only below 100kHz. This application note focuses on the significant differences between I2C and SMB. The I C bus and the SMBus are popular 2-wire buses that are essentially compatible with each other. Normally devices, both masters and slaves, are freely interchangeable between both buses. Both buses feature addressable slaves (although specific address allocations can vary between the two buses). The buses operate at the same speed, up to 100kHz, but the I C bus has both 400kHz and 2MHz versions. Obviously, complete compatibility between both buses using al
l devices is ensured only below 100kHz. This application note focuses on the significant differences between the two buses. Although it is assumed that the reader has some knowledge of the I C bus and/or the SMBus, let's first review some protocol basics:
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Start and Stop events. These are especially important in that they are ways of signaling to an interface that it needs to go to an initialized or reset state. Data and Clock must be high to generate Start and Stop. A master can't generate a Start or Stop unless both the Data (SDA for I C and SMBData for SMBus) and Clock (SCL for I C and SMBClk for SMBus) lines are free (not pulled low). This is a consequence of being an open-collector bus. Start and Stop conditions are the only times there will be a transition on the Data line while Clock is high. Data can change state only when Clock is low during a communication. The data on Data must always be ready just prior to a high on Clock and be changed only after Clock has gone low (with the exception of Start and Stop).
Figure 1. A typical communication, showing the Start and Stop conditions.
Timeout and Clock Speed
Timeout and (as a consequence of timeout) minimum clock speed are the most important differences between the I C bus and the SMBus.
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