AN564| Application Note
Maxim > App Notes > INTERFACE CIRCUITS
PROTECTION AND ISOLATION
Keywords: RS-232, rs232, tranceivers, EIA/TIA-232, ESD, protection diodes
Apr 06, 2001
APPLICATION NOTE 564
Tech Brief 10: ESD Considerations for RS-232 Drivers
Abstract: Technical brief suggests ESD protection schemes for RS-232 transceivers. Basic diode clamps, TransZorbTM, and zener diodes are considered. Internal latch-up is explained. Protection of vulnerable CMOS devices is a joint effort of a CMOS device manufacturer and the end product manufacturer using the device. Although input structures, such as clamp diodes, are making the devices less susceptible to ESD damage in a controlled production environment, the random nature of ESD events in enduser equipment requires additional protection devices. A choice or combination of the following devices improves product reliability, however there will always be a residual risk of ESD damage due to the unknown potential and energy of an ESD event. This tech brief introduces techniques to keep this risk low and explains the classical ESD-induced latch-up. The industry trend to process chips with ever-smaller chip geometries creates a greater sensitivity towards ESDrelated damage which offsets the gain of a smaller pac
kage and reduced board space. The level of protection has to increase with the likelihood of user access to the chips' terminals. As CMOS products have the highest input impedance, they are likely to collect charges and are prone to damage if no additional measures are taken to absorb those violent energies. Besides the ESD event that occurs when no power is supplied to the chip, a greater hazard exists when the circuit is powered. Charge injection can lead to a possible latch-up scenario which allows high current to flow from Vcc to GND, only limited by the on resistance of the latched FETs. Internal ESD structures, usually clamp diodes, will bypass overvoltage events to either Vcc or GND. Due to the amount of charge and the limited current-carrying capability of those structures, the charge floods the substrate with electrons and leads to a potential latch-up condition if power is applied. Due to the geometry of those ESD protection devcies, they will not be able to handle high currents for a sustained tim
e and energy absorption is marginal. Additional external devices are required to "take the heat" and prevent an ESD-induced latch-up: the Transient Voltage Suppressor diode (TVS).
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