app359| Application Note

Application Note 359 Interfacing the DS21x5y to the TMS320C54x
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INTRODUCTION
The TMS320C54x family of devices is fixed-point digital signal processors (DSP) offered by Texas Instruments. This family, referred to as `54x, implements several types of serial port operations. The buffered serial port, commonly referred to as the BSP, provide full-duplex communication capabilities with either a T1 or an E1 data structure, due to these ports supporting the use of frame synchronization strobes. The BSP allows transfers of 8-, 10-, 12-, or 16-bit data packets. In the continuous mode, the frame synchronization pulse occurs when the data transmission (or reception) is initiated. Any further pulses applied to this input during the reception or transmission of data packets will cause a receive or transmit abort condition, and one packet of data will be lost. In the burst mode, a frame synchronization pulse occurs for every packet. To ensure that each time slot of the T1 or E1 data stream is properly transferred between the `54x and the DS21x5y single-chip transceiver (SCT), this application note
outlines how to interconnect these two IC's for operation in both the continuous and burst modes.

TMS320C54x BSP Continuous Mode Operation
The continuous mode of operation in the `54x is selected by setting FSM = 0 in the Serial Port Control (SPC) register. The use of the Autobuffering Unit (ABU) is outlined here, as this will allow at least 125ms between BufferFull/Buffer Empty interrupts to the CPU. The minimal buffer size for either transmit or receive path would be 48 bytes, since there are 24 8-bit time slots per T1 frame (32 for E1). Please refer to Section 9.1 Introduction to the Serial Ports, of the TMS320C54x Reference Set, Volume 1: CPU and Peripherals for complete initialization and descriptions of BSP and ABU operations.

BCLKX BFSX

BDX

Figure 1. Continuous Mode Transmit Timing (External Frame) Note that in Figure 1, the Transmit synchronization pulse occurs at the location where the DS21x5y inserts a frame bit. Since the DS21x5y will internally generate the frame bit, and the `54x is not using the bit position where a frame synchronization pulse occurs, this allows a glueless interface between these two devices on this signal.

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