app393| Application Note
Application Note 393
E1 Operation of Dallas Semiconductor Framers and SCTs
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OVERVIEW
This application note covers five topics concerning Dallas Semiconductor framers and single-chip transceivers (SCTs). The first section provides a detailed explanation about how the framer or SCT synchronize to an incoming data stream. This section also defines the resync criteria and how a resync is performed. The second section explains how the framer or SCT can be set up to sync to a data stream when it is not known beforehand whether CAS or CRC4 multiframes are present in the data stream. The third section shows how a user can determine what frame or multiframe level caused a loss-ofsynchronization. The fourth section demonstrates how to decode the receive frame-error pin on a framer or SCT. Finally, the fifth section is a short tutorial on E1 frame and multiframe structures.
SECTION 1: HOW FRAMERS AND SCTs SYNC AND RESYNC
In an E1 mode, the data stream always contains the frame alignment signal (FAS), and it can contain either one or both of the two kinds of multiframe, namely cyclic redundancy check 4 (CRC4) and channel associated signaling (CAS). The following discussion covers how Dallas framers and SCTs handle synchronization and resynchronization under FAS, CRC4, and CAS levels. Refer to Figures 1A and 1B as a supplement to the discussion.
FAS Sync
The framer or SCT always begins a sync or resync with a search for the FAS. The framer or SCT considers that it has found the FAS when it has located a correct FAS word (X0011011), followed by a non-FAS word with bit 2 set to a 1 (X1XXXXXX), followed by another correct FAS word. If a proper FAS sequence exists in the incoming data stream, then the framer or SCT syncs to it in, at most, four frames or 500ms. If a resync is occurring (i.e., the part has previously obtained FAS sync), the framer or SCT begins a bit-by-bit search for the FAS word in the time slot following the one to which it had previously been aligned. This reduces the chance of the framer resyncing onto the same emulator. If both CAS and CRC4 are disabled, once the FAS sync criteria is met, the framer or SCT enters a sync condition and the receive loss-of-sync (RLOS) pin goes low. If either CAS or CRC4 is enabled, then the framer or SCT performs a search for its respective multiframe alignment signals before a sync condition is asserted. If b
oth CAS and CRC4 are enabled, then the searches are performed in parallel after the FAS sync criteria has been met.
CAS Multiframe Sync
If CAS is enabled, then the framer or SCT uses the frame alignment created by the FAS sync to locate time slot 16. The framer then begins searching time slot 16 for the multiframe alignment word (0000XXXX). If the framer or SCT finds the frame alignment word and the previous time slot 16 did not contain the multiframe alignment word, then CAS multiframe sync is declared. The user has the option of making the CAS sync criteria more rigid by setting the CAS multiframe sync criteria bit. If the multiframe sync criteria bit is set, then the framer or SCT looks for two additional multiframe alignment words before it declares sync. In the SYNC/RSYNC flow without the CAS multiframe-sync criteria bit set to low, if the framer or SCT cannot find CAS multiframe alignment in 12ms to 14ms (i.e., over six
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