AN-1098| Application Note

Loading PLL Frequency Synthesizers with COP8SAx7

Loading PLL Frequency Synthesizers with COP8SAx7
1.0 INTRODUCTION This application note describes the hardware and software required for loading Single or Dual Frequency Synthesizers for RF Communications with National Semiconductor's COP8TM family of microcontrollers. COP8SAx7 is an excellent choice for a low cost, single chip solution for configuring all parameters necessary for the frequency synthesizer. 2.0 DESIGN REQUIREMENTS This design example uses the LMX2320 Frequency Synthesizer and the COP8SAA7 Microcontroller. National's family of PLLatinumTM Frequency Synthesizers requires several registers to be loaded via a serial interface. (Please refer to the datasheets for the appropriate LMX PLL used in your design.) Registers to be configured include the Programmable Reference Divider (R Counter), the Prescaler Select (S Latch), and the Programmable Divider (N Counter). Data being sent to these registers are organized in "data streams." The datasheets for various PLL's will define the details, and bit placement, for these data streams. The microcontrol
ler must be able to transmit several data streams, control the LE (Load Enable) signal, and generate a clocking source. These "data streams" will be padded with leading zeroes, such the data streams are an integer multiple of eight (8, 16, 24, etc.) bits. After programming the PLL, the microcontroller will be placed in a power down mode, drawing virtually zero current from the circuit. The software is easily adaptable to allow the user to include many other functions. 3.0 FEATURES OF THE COP8SAx7 The COP8SAA716M9 was selected as the lowest cost solution. This is the 16-pin SOIC member of the COP8SAx7 One Time Programmable (OTP) family. Other COP8 family members would utilize the same source code. Several features of the COP8SAx7 are utilized in this design:

National Semiconductor Application Note 1098 Steven Goldman June 1998

3.2 Internal R/C COP8SAx7 includes an internal R/C oscillator circuit, eliminating the need for an external clock source, Crystal resonator, or external resistor and capacitor. This will save the system designer additional board space, and the expense of additional components. Since the serial interface is synchronized with a clock signal (CLOCK), the internal clock of the COP8SAx7 does not need to be excessively stable over temperature or time. Changes in clock stability are therefore ignored. The circuit can easily be modified to accept either clock input, external crystal or external R/C up to 10 MHz. Please refer to the COP8SAx7 Datasheet for further details. When programming the OTP COP8SAx7, please ensure that the "Internal R/C" option is selected. 3.3 Internal Pull-Up Resistors COP8SAx7 includes weak pull-up resistors on all input/ output ports. These are approximately 100k in value. The application circuit includes a jumper block (JP1) which selects the "DIAGNOSTIC" mode. The appropriate bit in the C
ONFIGURATION register for PORTG must be set to "0", to define that pin for input. The internal pull-up option is configured by writing a "1" to the corresponding bit in the DATA register for PORTG. For the application schematic shown this would be G0. Utilizing the internal pull-up once again saves the system designer the expense of an additional resistor on the final PCB, simplifies layout, and saves valuable board space. When the pin is left "floating", the software will read this input as "1." When JP1 is moved to GND, the pin will read as "0." 3.4 Power Down Mode After the software runs completely through, the COP8SAx7 will be placed in power down mode. Power consumption varies depending on the COP8 selected, but will be in the microamps range. Virtually zero. The system designer may choose to eliminate the power down aspect of the software provided. For many applications, COP8SAx7 will be performing other system tasks. 3.5 MICROWIRE Port Utilizing the MICROWIRE port, on the COP8SAx7, is the real heart o
f this design. All COP8 devices include on-board MICROWIRE hardware. This port consists of SI (Serial In), SO (Serial Out), and SK (Serial Clock). The SI pin is not used for this design. Details on operating MICROWIRE can be found in the COP8 Databook. A brief description is found below. Some LMX PLL's require a "data stream" of 22 bits, which have been rounded up to 24 bits, or 3 bytes. Each byte is loaded into the Serial Input/Output Register (SIOR). Setting the BUSY flag of the COP8's control register will initiate MICROWIRE transfer. Contents of the SIOR are then shifted out of pin G4/SO one bit at a time. The MICROWIRE hardware will also generate 8 clock pulses on the CLK pin (G5/ SK). After 8 bits have been shifted, the BUSY flag will be reset.

Power up Reset Internal R/C Internal Pull-Up Resistors Power Down Mode MICROWIRETM Port High Current Outputs

3.1 Power Up Reset COP8SAx7 includes internal reset circuitry. This eliminates the need for the traditional diode, capacitor, resistor circuit common to other COP8 family members, and other microcontrollers. Internal reset circuitry saves the system designer valuable board space and the expense of extra components. When the OTP COP8SAx7 is programmed, the "Internal Reset" option must be selected. The Application Schematic, Figure 1, shows the connection from the RESET pin to VCC. When programmed to utilize the internal circuit, the RESET pin must remain HIGH. Refer to the COP8SAx7 Datasheet for further details.

AN-1098

COP8TM, MICROWIRETM and PLLatinumTM are trademarks of National Semiconductor Corporation.

1999 National Semiconductor Corporation

AN100832

www.national.com