AN-1119| Application Note

Voltage Doubler Design and Analysis

Voltage Doubler Design and Analysis
INTRODUCTION Today's wireless applications demand lower operating voltages. A voltage doubler provides a means of obtaining a wider VCO tuning range at lower voltages. This paper discusses the considerations that need to be made when using a voltage doubler. Specific test results are shown for a CDMA application. The LMX2350 provides an internal switched capacitor voltage doubler circuit that allows the RF charge pump to operate close to twice the RF VCC voltage. An external capacitor, Cext, placed across the voltage doublers output, VP, is charged up by the internal switched capacitor switched on and off at the rate of the RF crystal oscillator frequency. The minimum allowable voltage droop will determine the size of the external capacitor. The amount of current the voltage doubler can deliver and still maintain its voltage is considerably smaller than the instantaneous current demanded by the charge pump when it is on. Therefore, a large external capacitor is needed to reduce the voltage droop. The time it
takes the voltage doubler to charge the external capacitor to twice VCC once the part is enabled is also set by the size of the external capacitor. Another consideration when using the voltage doubler is the average current required by the charge pump when the PLL is locked. This current will reduce the output voltage of the doubler. NOTE: For the LMX2350/52/54 Frequency Synthesizer Series, the voltage output of the doubler cannot exceed the 5.5 volts, which is the maximum specification for the RF charge pump power supply, VP. VOLTAGE DOUBLER CONCEPTS The voltage doubler uses a switched capacitor to double the supply voltage, shown in Figure 1.

National Semiconductor AN-1119 June 2001

AN101031-1

(a)

AN101031-15

(b) FIGURE 1. Voltage Doubler Switched Capacitor Circuit During the first half of the oscillator cycle switch S1 is closed, S2 is down and S3 is open, as shown in Figure 1a. This allows the internal capacitor to charge up to VCC. The second half of the oscillator cycle switch S1 is open, S2 is up, and S3 is closed, as shown in Figure 1b. This places the voltage on the internal capacitor in series with the supply voltage. Charge is redistributed to the external capacitor, Cext. The internal switched capacitor can be ideally represented as a resistor and a voltage source as shown in Figure 2.

AN-1119

2001 National Semiconductor Corporation

AN101031

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