AN-1263| Application Note

DP83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer Design Guide

DP83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer Design Guide
1.0 Introduction
This design guide is intended to assist in the circuit design and board layout of the DP83865 Gigabit Ethernet physical layer transceiver. This design guide covers the following subjects: Hardware Reset and Start Up Clocks

National Semiconductor Application Note 1263 Leo Chang December 2003

RESET input. The active low RESET should be held low for a minimum of 150 us to allow power supply voltage and clock input to stablize before starting internal initialization. The first MDIO access should wait another 500 us till internal initialization is completed. For timing details see 7.0 Layout Notes on MAC Interface of the datasheet.

3.0 Clocks
The CLOCK_IN pin is the 25 MHz clock input to the DP83865 used by the internal PLL to generate various clocks needed internally and externally. This input should come from a 25 MHz clock oscillator or crystal. (Check 12.0 Component Selection for component requirements.) When using a crystal, CLOCK_OUT must be connected to the second terminal, and when using with a oscillator the CLOCK_OUT pin should be left floating.

Power Supply Decoupling Sensitive Supply Pins PCB Layer Stacking Layout Notes on MAC Interface Twisted Pair Interface RJ-45 Connections Unused Pins/ Reserved Pins Component Selection

2.0 Hardware Reset and Start Up
There is no on-chip internal power-on reset and the DP83865 requires an external reset signal applied to the

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FIGURE 1. Clock Input Circuit The clock signal requires termination consideration. The termination requirement depends on the trace length of the clock signal. No series or load termination is required for short trace less than 0.5 inch. For longer traces termination resistors are recommended. There are a number of ways to terminate clock traces. The commonly used types are series and parallel termination. Series termination consumes less power and it is the recommended termination. The value of the series termination resistor is chosen to match the trace characteristics impedance. For example, if the clock source has output impedance of 20 and the clock trace has characteristic impedance Zo = 50 then Rs = 50 - 20 = 30 . The series source termination Rs should be placed close to the output of the crystal oscillator. The parallel termination consumes more power than series termination, but yields faster rise and fall times. The value of the termination is equal to the trace characteristic impedance, RT = Zo
. The parallel termination RT should be placed close to the PHY CLOCK_IN pin to eliminate reflections. In cases where multiple PHY's exist on the same board, it may be cost effective to use one oscillator with a high speed PLL clock distribution driver. Connecting multiple clock inputs in a Daisy chained style should be avoided, especially when series termination is applied. Adequate and proper decoupling is important to the clock oscillator performance. A multilayer ceramic chip capacitor should be placed as close to the oscillator VDD pin as possible to supply the transient switching current. EMI is another consideration when designing the clock circuitry. The EMI field strength is proportional to the current flow, frequency, and loop area. By applying series termination, the current flow is less than parallel termination and the edge speed is slower, making it better for EMI considerations. Loop area is defined as the trace length times the

AN-1263

2003 National Semiconductor Corporation

AN200567

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