AN-1480| Application Note

AN-1480 PDF

AN-1480| Application Note


LP38859S-1.2 Evaluation Board

LP38859S-1.2 Evaluation Board
Introduction
This board is designed to enable the evaluation of the LP38859 Voltage Regulator. Each board is assembled and tested in the factory. This evaluation board has the TO-263 5 lead package mounted.

National Semiconductor Application Note 1480 Don Jones November 2006

Soft-Start Time = 5 x rSS x CSS The installed soft-start capacitor (CSS) is 10 nF (0.01 uF), and the internal rSS is typically 16 k.

General Description
The LP38859 is a dual-rail LDO linear regulator capable of supplying up to 3A of output current, and incorporates a Soft-Start feature. The device has been designed to work with 10 uF input and output ceramic capacitors, and 1uF bias capacitors. Footprints areas for CIN and COUT will allow for a variety of sizes.

Operation
The input voltage, applied between VIN and GND, should be at least 1.0V greater than VOUT, and no higher than the applied VBIAS voltage. The bias voltage, applied between VBIAS and GND should be above the minimum bias voltage of 3.0V, and no higher than the maximum of 5.5V. Loads can be connected to VOUT with reference to GND. VOUT and VIN test points are provided on the board to allow accurate measurements directly on the evaluation board, eliminating any voltage drop on the PCB traces or connecting wires to the load. The Soft-Start time for VOUT is an exponential function, and is adjusted by changing the Soft-Start capacitor (CSS) on device pin one. An internal resistor (rSS) and the external capacitor (CSS) form an RC circuit. Five RC time constants is considered to be the Soft-Start time.

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FIGURE 1. VOUT vs CSS

Hardware
The schematic and layout of the evaluation board are given below:

Schematic Diagram

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Evaluation Board Schematic

AN-1480

2006 National Semiconductor Corporation

AN201936

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