AN-1504| Application Note
LP38853S-ADJ Evaluation Board
LP38853S-ADJ Evaluation Board
National Semiconductor Application Note 1504 Don Jones January 2007
Introduction
This board is designed to allow the evaluation of the LP38853S-ADJ Voltage Regulator. Each board is assembled and tested in the factory. This evaluation board has the TO-263 7-lead package mounted, and the output voltage is set to 1.20V.
CFF = 1 / (2 x x FZ x R1)
(3)
The closest standard 10% value is usually adequate for CFF. The LP38853-ADJ Evaluation board is assembled with a 0.01 F capacitor for CFF. This sets FZ to approximately 11.4 kHz.
General Description
The LP38853 is a dual-rail adjustable LDO linear regulator capable of suppling up to 3A of output current, and incorporates an Enable function as well as a Soft-Start function. The device has been designed to work with 10 uF input and output ceramic capacitors, and 1uF bias capacitor. Footprints areas for CIN and COUT will allow for a variety of sizes.
Operation
The input voltage, applied between VIN and GND, should be at least 1.0V greater than VOUT and no greater than the applied VBIAS voltage. The bias voltage, applied between VBIAS and GND should be above the minimum bias voltage of 3.0V, and no more than the maximum of 5.5V. Loads can be connected to VOUT with reference to GND. VOUT and VIN test points are provided on the board to allow accurate measurements directly onto the input and output pins of the device, eliminating any voltage drop on the PCB traces or connecting wires to the load.
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FIGURE 1. 10mA to 3A Load Transient Response
Setting VOUT
The output voltage is set using the external resistive divider R1 and R2. The output voltage is given by the formula: VOUT = VADJ x (1 + (R1 / R2)) (1)
It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 10 k. This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the FZ pole set by R1 and CFF. The LP38853S-ADJ Evaluation board is assembled with a 1.40 k 1% resistor for R1, and a 1.00 k 1% resistor for R2. This sets VOUT to 1.20V.
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Selecting CFF
A capacitor placed across the gain resistor R1 will provide additional phase margin to improve load transient response of the device. This capacitor, CFF, in parallel with R1, will form a zero in the loop response given by the formula: FZ = (1 / (2 x x CFF x R1) ) (2)
FIGURE 2. 1A to 3A Load Transient Response
Enable Function
ON/OFF control is provided by supplying a logic level signal to the Enable pin. A minimum VEN value of 1.3V is typically required at this pin to enable the LDO output. The LDO output will be shutdown when the VEN value is typically 1.0V or less. The VEN threshold incorporates approximately 100mV of hysteresis. In applications where the LP38853 is operated continuously the Enable pin can be connected directly to VBIAS, or left open.
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AN-1504
The value for CFF should be selected to set a zero frequency (FZ) between 10 kHz and 15 kHz using the formula:
2007 National Semiconductor Corporation
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