AN-1854| Application Note

DP83848C PHYTER Single to DP83848J/M PHYTER Mini System Rollover Document

DP83848C PHYTER Single to DP83848J/M PHYTER Mini System Rollover Document
Purpose
This is an informational document detailing points to be considered when migrating an existing 10/100 Mb/s Ethernet design using the National Semiconductor DP83848C PHYTER product to the smaller DP83848J or DP83848M products. The DP83848C and DP83848J/M feature the following: Support 10/100 MII interface Operation over the commercial temperature range Compliant with IEEE 802.3 specification This document compares differences including feature set, pin functions, package and pinout, and possible register operation differences between DP83848C and DP83848J/M to simplify end user setup and help ensure a better user experience. The impact to a design is dependant on features used and their implementation.

National Semiconductor Application Note 1854 Devin Seely September 3, 2008

(10uF Tantalum and 0.1uF ceramic) should be placed close to PFBOUT, the output of the regulator. PFBIN1 and PFBIN2 should be externally connected to PFBOUT as shown in Figure 1. A small 0.1uF capacitor should be placed close to the PFBIN1 and PFBIN2 pins. The pin assignment differences between the DP83848C and DP83848J/M are summarized in Table 2.

1.0 Required Changes
This section documents the hardware changes required to transition from the DP83848C to the DP83848J or DP83848M. The required changes for proper operation include package, pinout, bias and termination connections. 1.1 PACKAGE The DP83848C is available in a 48 pin LQFP package. The DP83848J/M comes in a 40 pin LLP package. The differences in package between DP83848C and DP83848J/M are shown in Table 1. For more information on the DP83848 packages please visit http://www.national.com/analog/packaging/ TABLE 1. Packaging Differences DP83848C Package Footprint Package Drawing 48-LQFP 7x7 mm VBH48A DP83848J/M LLP 40 6x6 mm SQA40A
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FIGURE 1. PFBOUT Connection TABLE 2. Power Feedback Connections Signal Name PFBOUT PFBIN1 PFBIN2 DP83848C 23 18 37 DP83848J/M 19 16 30

1.3.2 Bias Resistor Internal circuitry biasing for the devices is accomplished in a similar manner. The only difference is the bias connection pin number. The 4.87 kohm connects to pin 24 on the DP83848C and pin 20 on the DP83848J/M. TABLE 3. Bias Resistor Values DP83848C Bias Resistor Value Bias Pin 4.87 kohm 24 DP83848J/M 4.87 kohm 20

1.2 PINOUT The DP83848C has 48 pins while the DP83848J/M have a reduced pin count. The LLP package used on the DP83848J/ M also has an exposed DAP pad. Please see Appendix A for the pin mapping between DP83848C and DP83848J/M, as well as pins not applicable in the DP83848J/M. 1.3 PCB MODIFICATION This section describes the DP83848C circuit modifications required to use the DP83848J/M in a similar design. 1.3.1 PFBOUT Both the DP83848C and DP83848J/M devices require similar connection of the Power Feedback circuit. Parallel capacitors

1.3.3 Termination and PMD Biasing DP83848C and DP83848J/M PMD interface require two pair of 49.9 Ohm resistors, biased to VDD of the device. This matching of the termination resistors and common biasing between the receiver and transmitter accommodates the Auto-MDIX feature. Refer to Figure 2 for a graphic explanation of this.

AN-1854

PHYTER is a registered trademark of National Semiconductor.

2008 National Semiconductor Corporation

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