AN-247| Application Note

Using the ADC0808/ADC0809 8-Bit uP Compatible A/D Converters with 8-Channel Analog Multiplexer

Using the ADC0808/ADC0809 8-Bit uP Compatible A/D Converters with 8-Channel Analog Multiplexer
Introduction
The ADC0808/ADC0809 Data Acquisition Devices (DAD) implement on a single chip most the elements of the standard data acquisition system. They contain an 8-bit A/D converter, 8-channel multiplexer with an address input latch, and associated control logic. These devices provide most of the logic to interface to a variety of microprocessors with the addition of a minimum number of parts. These circuits are implemented using a standard metal-gate CMOS process. This process is particularly suitable to applications where both analog and digital functions must be implemented on the same chip. These two converters, the ADC0808 and ADC0809, are functionally identical except that the ADC0808 has a total unadjusted error of 1/2 LSB and the ADC0809 has an unadjusted error of 1 LSB. They are also related to their big brothers, the ADC0816 and ADC0817 expandable 16 channel converters. All four converters will typically do a conversion in 100 us when using a 640 kHz clock, but can convert a single input in as little as
50 us.

National Semiconductor Application Note 247 Larry Wakeman September 1980

Functional Description
The ADC0808/ADC0809, shown in Figure 1, can be functionally divided into 2 basic subcircuits. These two subcircuits are an analog multiplexer and an A/D converter. The multiplexer uses 8 standard CMOS analog switches to provide for up to 8 analog inputs. The switches are selectively turned on, depending on the data latched into a 3-bit multiplexer address register.

The second function block, the successive approximation A/D converter, transforms the analog output of the multiplexer to an 8-bit digital word. The output of the multiplexer goes to one of two comparator inputs. The other input is derived from a 256R resistor ladder, which is tapped by a MOSFET transistor switch tree. The converter control logic controls the switch tree, funneling a particular tap voltage to the comparator. Based on the result of this comparison, the control logic and the successive approximation register (SAR) will decide whether the next tap to be selected should be higher or lower than the present tap on the resistor ladder. This algorithm is executed 8 times per conversion, once every 8 clock periods, yielding a total conversion time of 64 clock periods. When the conversion cycle is complete the resulting data is loaded into the TRI-STATE output latch. The data in the output latch can then be read by the host system any time before the end of the next conversion. The TRI-STATE capabil
ity of the latch allows easy interface to bus oriented systems. The operation of these converters by a microprocessor or some control logic is very simple. The controlling device first selects the desired input channel. To do this, a 3-bit channel address is placed on the A, B, C input pins; and the ALE input is pulsed positively, clocking the address into the multiplexer address register. To begin the conversion, the START pin is pulsed. On the rising edge of this pulse the internal registers are cleared and on the falling edge the start conversion is initiated.

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FIGURE 1. ADC0808/ADC0809 Functional Block Diagram

AN-247

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2002 National Semiconductor Corporation

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