AN-834| Application Note

Live Insertion with BTL Transceivers

Live Insertion with BTL Transceivers
This paper investigates the possible glitches caused by inserting a board or module into a powered Futurebus+ backplane. The signal lines on the backplane will be in one of three states; high -- when the bus is released, low -- when the bus is asserted, and the transition state. In the transition state the bus will be going from a high to a low state or vice versa. The bus will spend the majority of the time in the high or low state. The glitch during live insertion will be investigated for the high and low state. The LI (live insertion) pin on the Futurebus+ Transceivers helps minimize the loading on the bus during live insertion and after the board has been plugged into the backplane.

National Semiconductor Application Note 834 Joel Martinez Stephen Kempainen July 1992

When LI is connected to VCC and the output is in the released state, the output Schottky diode (DS2) remains reversed biased thereby minimizing the output capacitance as shown below. Reducing the capacitance at the output will minimize bus loading. The measurements were taken from a 10 slot backplane with 1" slot to slot spacing. The lines were terminated with 39 resistors to 2.1V at each end. This is not a Profile A/B/F compliant Futurebus+ backplane. A standard backplane will have 30 mm (11/4") slot to slot spacing, 14 slots and 33 terminations. The board was provided by Hybricon and uses the DS3884A Futurebus+ 6-bit transceiver offered by National Semiconductor. The live insertion glitch taken on this backplane will be similar if taken on a standard Futurebus+ backplane. The measurements were taken directly on the backplane (the rear side of the backplane was probed using a high impedance 2 GHz scope) unless otherwise specified. The Futurebus+ backplane has two stages of contact. Stage one is when the pow
er pins between the board and the backplane mate. Stage two is when the rest of the signal pins make contact. These two stages are implemented by having short signal pins and long power pins on the backplane. As the board is inserted into the backplane the backplane power pins (VBP and ground) make contact with the board sooner than the signal pins as shown on Figure 1 . Stage two, when the signal pins make contact with the backplane, will be the subject of this paper.

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AN-834

1998 National Semiconductor Corporation

AN011482

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