rej05b0280_m16cap| Application Note
APPLICATION NOTE
M16C/62A Group
Error-permitted range of transfer baud (UART)
1. Abstract
The following article introduces error-permitted range of transfer baud (UART).
2. Introduction
The explanation of this issue is M16C/62A Group.
3. Error-permitted range of transfer baud
During reception, the receive data input to the RXDi pin is taken at the rising edge of the transfer clock. Accordingly, in order to receive data correctly, the stop bit must be input when the transfer clock of oneset receive data rises last. Figure 1 shows the relationship between the transfer clock and receive data.
<1ST-8DATA-1SP>
When the transfer rate of the receive data is faster than the rate of the transfer clock on the receiver side When the transfer rate of the receive data is slower than the rate of the transfer clock on the receiver side Transfer clock (Receiver side) 1 clock 8 clocks 9.5 clocks 1 period of BRGi's count source (Maximum) According to the condition of the input timing, a maximum of this period () can be omitted. ST : Start bit SP : Stop bit
ST ST
D0 D0
D7 D7
SP SP
SP must be detected at this last rising edge of the transfer clock.
RxDi (Receive data)
At the falling edge of ST, the transfer clock is generated, and reception starts.
1 clock
Figure 1. Relationship between transfer clock and receive data
Accordingly, the transfer rate of the receiver and transmitter sides must satisfy the following fomula in order to receive data correctly.
1 Bt
x (b 1) +
1 F
<
1 Br
x (b 0.5) +
1 F
<
1 Bt
xb
Br : Transfer rate on receiver side (bps) Bt : Transfer rate on transmitter side (bps) F : BRGi's count source frequency on receiver side (Hz) b : Entire bit number of one-set data (However, "-1" for 2SP) (ex : 11 bits in the case of 1ST-8DATA-1PAR-2SP; See Figure 2) Be sure to satisfy the above formula, and set the timing with enough margin. Also, the user shall make sufficient evaluation before actually using it.
REJ05B0280-0101/Rev.1.01
November 2006
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