rej05b0602_m16cap| Application Note
APPLICATION NOTE
M32C/83, M32C/84 Group
Differences between M32C/83 and M32C/84
1. Abstract
The following document describes differences between M32C/83 and M32C/84.
2.
Introduction
The explanation of this issue is applied to the following condition: Applicable MCU: M32C/83, M32C/84 Group
3.
Contents
3.1 Function Differences
Table 3.1.1 and Table 3.1.3 show the Function Differences. Table 3.1.1 Function Differences (1/3) (Note1)
Item I/O power supply Supply Voltage M32C/83 Single (VCC) 4.2V to 5.5V (f(BCLK))=32MHz) 3.0V to 5.5V (f(BCLK))=20MHz, VDC on) 3.0V to 3.6V (f(BCLK))=20MHz, VDC off) None None 41mA(VCC=5V, f(BCLK)=32MHz) 26mA(VCC=3.3V, f(BCLK)=20MHz) 470uA(VCC=5V, f(BCLK)=32kHz, in wait mode) 5.0uA(VCC=3.3V, f(BCLK)=32kHz, VDC off, in wait mode) 0.4uA (in stop mode) No wait to 3 waits (Select WCR register) Not available Can be set for CM0, CM1, CM2, MCD, PLC0, PLC1, PM0, PM1, INVC0, INVC1, PD9, PS3, PLV, VDC0 register Set in four addresses Falling edge ________ edges of input signals to or both ________ the INT0 to INT3 pin Timer A0 to timer A4 interrupt requests Timer B0 to timer B5 interrupt requests UART0 to UART4 transmit and receive interrupt requests A/D0 conversion interrupt request A/D1 conversion interrupt request Intelligent I/O interrupt request 0 to 11 CAN interrupt request Software trigger M32C/84 M32C/84 Double (VCC1 VCC2) M32C/84T Single (VCC1 = VCC2) VCC1=4.2V to 5.5V, VCC2=3.0V (f(BCLK)=32MHz) VCC1=3.0V to 5
.5V, VCC2=3.0V (f(BCLK)=24MHz) Have
to to
VCC1 VCC1
System Clock Protect Function Voltage Detection Circuit Power Consumption
Bus Wait Recovery Cycle Protect
M32C/84 Have M32C/84T None 28mA (VCC1= VCC2=5V, f(BCLK)=32MHz) 22mA (VCC1= VCC2=3.3V, f(BCLK)=24MHz) 10uA (VCC1= VCC2=5V, f(BCLK)=32kHz, in wait mode) 10uA (VCC1= VCC2=3.3V, f(BCLK)=32kHz, in wait mode) 0.8uA (in stop mode) 1 wait to 8 waits (Select EWCR0 to EWCR3 register) Available Can be set for CM0, CM1, CM2, MCD, PLC0, PLC1, PM0, PM1, INVC0, INVC1, PD9, PS3, PM2, VCR2, D4INT register Set in eight addresses The next interrupt is deleted from M32C/83. A/D1 conversion interrupt request Intelligent I/O interrupt request 5 to 7
Address Match Interrupt DMA Request Factors
Note 1: About the details and the characteristics, refer to hardware manual.
REJ05B0602-0100/Rev.1.00
April 2005
Page 1 of 13
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