rej05b0772_3850aap| Application Note
APPLICATION NOTE
3850 Group (Spec.A)
List of Registers
1. Abstract
The following article describes the control registers of the 3850 Group (Spec.A).
2. Introduction
The explanation of this issue is applied to the following condition: Applicable MCU: 3850 Group (Spec.A)
3. Structure of Register
The figure of each register structure describes its functions, contents at reset, and attributes as follows:
(Note 2)
Bits
b7 b6 b5 b4 b3 b2 b1 b0 0
Bit attributes
(Note 1)
Contents immediately after reset release
CPU mode register (CPUM) [Address : 3B16] B 0 1 2 3 4 5 6 7 Stack page selection bit Name Processor mode bits
b1 b0
Function
0 0 : Single-chip mode 01: 1 0 : Not available 11: 0 : 0 page 1 : 1 page
At reset
R W
0 0 0 0 0 1
Nothing arranged for these bits. These are write disabled bits. When these bits are read out, the contents are "0." Fix this bit to "0." Main clock (XIN-XOUT) stop bit Internal system clock selection bit
0 : Operating 1 : Stopped 0 : XIN-XOUT selected 1 : XCIN-XCOUT selected
: Bit in which nothing is arranged
: Bit that is not used for control of the corresponding function
Note 1:. Contents immediately after reset release 0....... "0" at reset release 1....... "1" at reset release ?....... Undefined at reset release .......Contents determined by option at reset release Note 2: Bit attributes......... The attributes of control register bits are classified into 3 bytes : read-only, writeonly and read and write. In the figure, these attributes are represented as follows : R....... Read ...... Read enabled .......Read disabled W......Write ..... Write enabled ...... Write disabled
REJ05B00772-0100/Rev1.00
November 2005
Page 1 of 20
rej05b0772_3850aap Application Note renesas Download PDF
Add this permalink to your bookmarks for future download of rej05b0772_3850aap ApplicationNote
Permalink: http://application.emcelettronica.com/renesas/rej05b0772_3850aap
